CY7C4291 Datasheet, PDF (13/16 Pages) Cypress Semiconductor – 64K/128K x 9 Deep Sync FIFOs

Switching Waveforms (continued)
Programmable Almost Full Flag Timing
t_CLKH
t_CLKL
WCLK
WEN1
t_ENS t_ENH
WEN2
(if applicable)
PAF
t_ENS t_ENH
FULL − (M+1)WORDS
IN FIFO
RCLK
REN1,
REN2
[23]
Note 24
t_PAF
(FULL −M) WORDS
IN FIFO ^[25]
t_SKEW2 ^[26]
t_ENS
t_ENS t_ENH
CY7C4281
CY7C4291
t_PAF
Write Programmable Registers
t_CLKH
t_CLK
t_CLKL
WCLK
WEN2/LD
t_ENS
t_ENH
WEN1
t_ENS
t_DS
t_DH
D₀ –D₈
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
Notes:
23. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW.
24. PAF offset = m.
25. 16,384 − m words for CY7C4281, 32,768 − m words for CY4291.
26. t_SKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and
the rising edge of WCLK is less than t_SKEW2, then PAF may not change state until the next WCLK.
Document #: 38-06007 Rev. *B
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