CY7C2263XV18 Datasheet, PDF (13/29 Pages) Cypress Semiconductor – 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

CY7C2263XV18, CY7C2265XV18
TAP Controller State Diagram
The state diagram for the TAP controller follows. ^[14]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
1
IDLE
SELECT
1
DR-SCAN
0
1
CAPTURE-DR
0
SHIFT-DR
0
1
1
EXIT1-DR
0
PAUSE-DR
0
1
0
EXIT2-DR
1
UPDATE-DR
1
0
1
SELECT
IR-SCAN
0
1
CAPTURE-IR
0
SHIFT-IR
0
1
1
EXIT1-IR
0
PAUSE-IR
0
1
0
EXIT2-IR
1
UPDATE-IR
1
0
Note
14. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-70331 Rev. *B
Page 13 of 29