CY7C1460AV33_11 Datasheet, PDF (13/28 Pages) Cypress Semiconductor – 36-Mbit (1 M x 36/2 M x 18) Pipelined SRAM with NoBL Architecture

CY7C1460AV33
CY7C1462AV33
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The boundary scan register has a special bit located at bit #89
(for 165-ball FBGA package) or bit #138 (for 209-ball FBGA
package). When this scan cell, called the “extest output bus
tristate,” is latched into the preload register during the
“Update-DR” state in the TAP controller, it directly controls the
state of the output (Q-bus) pins, when the EXTEST is entered as
the current instruction. When HIGH, it enables the output buffers
to drive the output bus. When LOW, this bit places the output bus
into a high Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is preset HIGH
to enable the output when the device is powered-up, and also
when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing Diagram
1
2
3
4
5
6
Test Clock
(TCK )
Test M ode Select
(TM S)
tTH
tTL
tTM _SS tTM _SH
tCY _C
tTDIS tTDIH
Test Data-In
(TDI)
tTDOV
Test Data-Out
(TDO)
tTDOX
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range^{[12, 13]}
Parameter
Description
Min
Clock
t_TCYC
TCK clock cycle time
50
t_TF
TCK clock frequency
–
t_TH
TCK clock HIGH time
20
t_TL
TCK clock LOW time
20
Output Times
t_TDOV
TCK clock LOW to TDO valid
–
t_TDOX
TCK clock LOW to TDO invalid
0
Setup Times
t_TMSS
TMS setup to TCK clock rise
5
t_TDIS
TDI setup to TCK clock rise
5
t_CS
Capture setup to TCK rise
5
Hold Times
t_TMSH
TMS hold after TCK clock rise
5
t_TDIH
TDI hold after clock rise
5
t_CH
Capture hold after clock rise
5
Notes
12. t_CS and t_CH refer to the setup and hold time requirements of latching data from the boundary scan register.
13. Test conditions are specified using the load in TAP AC test Conditions. t_R/t_F = 1 ns.
Max
Unit
–
ns
20
MHz
–
ns
–
ns
10
ns
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
Document Number: 38-05353 Rev. *I
Page 13 of 28
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