CY28551 Datasheet, PDF (13/30 Pages) Cypress Semiconductor – Universal Clock Generator for Intel, VIA, and SIS®

CY28551
Crystal Recommendations
The CY28551 requires a parallel resonance crystal. Substi-
tuting a series resonance crystal will cause the CY28551 to
operate at the wrong frequency and violate the ppm specifi-
cation. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It is a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Figure 1. Crystal Capacitive Clarification
Figure 2. Crystal Loading Example
Clock Chip
C i1
C i2
Pin
3 to 6p
X1
Cs1
X2
Cs2
XTAL
Trace
2.8 pF
Ce1
Ce2
Trim
33 pF
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
CLe
=
1
(
Ce1
+
1
Cs1
+
Ci1
+
Ce2
+
1
Cs2
+
Ci2
)
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
CL ....................................................Crystal load capacitance
CLe ......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce ..................................................... External trim capacitors
Cs ..............................................Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
Multifunction Pin Selection
In the CY28551, some of the pins can provide different types
of frequency, depending on the SEL[1:0] HW strapping pin
setting, to support different chipset vendors. The configuration
is shown as follows:
SEL[1:0]
00
01
10
11
LINK/DOT/SA
TA
LINK
DOT
LINK
SATA
SATA/PCIE
SATA
SATA
PCIEX
PCIEX
Platform
SIS
Intel W/Gfx
VIA
Intel
Document #: 001-05675 Rev. *C
Page 13 of 30