CY14MB064J1A Datasheet, PDF (13/28 Pages) Cypress Semiconductor – 64-Kbit (8 K × 8) Serial (I2C) nvSRAM

CY14MB064J1A/CY14MB064J2A
PRELIMINARY _{CY14ME064J1A/CY14ME064J2A}
By Master
SDA Line
By nvSRAM
Figure 19. Random Address Multi-Byte Read (except Hs-mode)
S
T
A
R _{Memory Slave Address}
T
Most Significant Address
Byte
Least Significant Address
Byte
Memory Slave Address
S 1 0 1 0 A2 A1 A0 0
X XX
Sr 1 0 1 0 A2 A1 A0 1
A
S
A
A
A
T
A₀
P
P
Data Byte N
A
Data Byte 1
Figure 20. Random Address Single-Byte Read (Hs-mode)
By Master
SDA Line
By nvSRAM
S
T
A
R _{Hs-mode command}
T
S00 0 01 XX X
Memory Slave Address
Sr 1 0 1 0 A2 A1 A0 0
Most Significant Address
Byte
X XX
Least Significant Address
Byte
Memory Slave Address
Sr 1 0 1 0 A2 A1 A0 1
A
A
A
A
A
S
T
A0
P
P
Data Byte
By Master
SDA Line
By nvSRAM
S
T
A
R _{Hs-mode command}
T
S00 0 01 XX X
Figure 21. Random Address Multi-Byte Read (Hs-mode)
Memory Slave Address
Most Significant Address
Byte
Sr 1 0 1 0 A2 A1 A0 0 X X X
Least Significant Address
Byte
Memory Slave Address
Sr 1 0 1 0 A2 A1 A0 1
A
A
A
A
A
S
T
A
A0
P
P
Data Byte
Data Byte N
Document Number: 001-70393 Rev. *E
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