CY14C256PA Datasheet, PDF (13/44 Pages) Cypress Semiconductor – 256-Kbit (32 K x 8) SPI nvSRAM with Real Time Clock Infinite read, write, and RECALL cycles

CY14C256PA
CY14B256PA
CY14E256PA
From the subsequent falling edge of the SCK, the data of the
specific address is shifted out serially on the SO line starting with
MSB. The first byte specified can be at any location. The device
automatically increments to the next higher address after each
byte of data is output. The entire memory array can therefore be
read with a single FAST_READ instruction. When the highest
address in the memory array is reached, address counter rolls
over to start address 0x0000 and thus allowing the read
sequence to continue indefinitely. The FAST_READ instruction
is terminated by driving CS HIGH at any time during data output.
Note FAST_READ instruction operates up to maximum of
104 MHz SPI frequency.
Write Sequence (WRITE) Instruction
The write operations on CY14X256PA are performed through the
SI pin. To perform a write operation, if the device is write
disabled, then the device must first be write enabled through the
WREN instruction. When the writes are enabled (WEN = ‘1’),
WRITE instruction is issued after the falling edge of CS. A
WRITE instruction constitutes transmitting the WRITE opcode
on SI line followed by 2-bytes of address and the data (D7-D0)
which is to be written. The MSB bit (A15) of the address is a
“don’t care”.
CY14X256PA allows writes to be performed in bursts through
SPI which can be used to write consecutive addresses without
issuing a new WRITE instruction. If only one byte is to be written,
the CS line must be driven HIGH after the D0 (LSB of data) is
transmitted. However, if more bytes are to be written, CS line
must be held LOW and address incremented automatically. The
following bytes on the SI line are treated as data bytes and
written in the successive addresses. When the last data memory
address (0x7FFF) is reached, the address rolls over to 0x0000
and the device continues to write.
The WEN bit is reset to ‘0’ on completion of a WRITE sequence.
Note When a burst write reaches a protected block address, it
continues the address increment into the protected space but
does not write any data to the protected memory. If the address
roll over takes the burst write to unprotected space, it resumes
writes. The same operation is true if a burst write is initiated
within a write protected block.
Figure 11. Read Instruction Timing
CS
SCK
SI
SO
0 1 2 34 5 67 0 1 23 45 6 7
12 13 14 15 0 1 2 3 4 5 6 7
Op-Code
15-bit Address
0 0 0 0 0 0 1 1 X A14 A13 A12 A11 A10 A9 A8
MSB
A3 A2 A1 A0
LSB
HI-Z
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Data
LSB
Figure 12. Burst Mode Read Instruction Timing
CS
SCK
SI
SO
01 2 3 456 7 01 2 3 45 6 7
12 13 14 15 0 1 2 3 4 5 6 7 0 7 0 1 2 3 4 5 6 7
Op-Code
15-bit Address
0 0 0 0 0 0 1 1 X A14 A13 A12 A11 A10 A9 A8
MSB
A3 A2 A1 A0
LSB
Data Byte 1
Data Byte N
HI-Z
D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
MSB
LSB
Document #: 001-65281 Rev. *B
Page 13 of 44
[+] Feedback