CY14B512P Datasheet, PDF (13/36 Pages) Cypress Semiconductor – 512-Kbit (64 K × 8) Serial (SPI) nvSRAM with Real Time Clock

CY14B512P
READ RTC (RDRTC) Instruction
Read RTC (RDRTC) instruction allows the user to read the
contents of RTC registers. Reading the RTC registers through
the SO pin requires the following sequence: After the CS line is
pulled LOW to select a device, the RDRTC opcode is transmitted
through the SI line followed by eight address bits for selecting the
register. Any data on the SI line after the address bits is ignored.
The data (D7-D0) at the specified address is then shifted out onto
the SO line. RDRTC also allows burst mode read operation.
When reading multiple bytes from RTC registers, the address
rolls over to 0x00 after the last RTC register address (0x0F) is
reached.
The ‘R’ bit in RTC flags register must be set to '1' before reading
RTC time keeping registers to avoid reading transitional data.
Modifying the RTC flags register requires a Write RTC cycle. The
R bit must be cleared to '0' after completion of the read operation.
The easiest way to read RTC registers is to perform RDRTC in
burst mode. The read may start from the first RTC register (0x00)
and the CS must be held LOW to allow the data from all 16 RTC
registers to be transmitted through the SO pin.
Note Read RTC (RDRTC) instruction operates at a maximum
clock frequency of 25 MHz. The opcode cycles, address cycles
and data out cycles need to run at 25 MHz for the instruction to
work properly.
Figure 14. Read RTC (RDRTC) Instruction Timing
CS
SCK
SI
SO
0 1 2 34 5 67 0 1 2 3 4 5 670 1 2 34 5 67
Op-Code
0 0 0 1 _{0 0 1} 1 _{0 0 0 0 A3 A2 A1 A0}
MSB
LSB
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Data
LSB
WRITE RTC (WRTC) Instruction
WRITE RTC (WRTC) instruction allows the user to modify the
contents of RTC registers. The WRTC instruction requires the
WEN bit to be set to '1' before it can be issued. If WEN bit is '0',
a WREN instruction needs to be issued before using WRTC.
Writing RTC registers requires the following sequence: After the
CS line is pulled LOW to select a device, WRTC opcode is
transmitted through the SI line followed by eight address bits
identifying the register which is to be written to and one or more
bytes of data. WRTC allows burst mode write operation. When
writing more than one registers in burst mode, the address rolls
over to 0x00 after the last RTC address (0x0F) is reached.
Note that writing to RTC timekeeping and control registers
require the W bit to be set to '1'. The values in these RTC
registers take effect only after the ‘W’ bit is cleared to '0'. Write
Enable bit (WEN) is automatically cleared to ‘0’ after completion
of the WRTC instruction.
Figure 15. Write RTC (WRTC) Instruction Timing
CS
SCK
0 1 2 34 5 67 0 1 2 3 4 5 670 1 2 34 5 67
Op-Code
4-bit Address
SI
0 0 0 1 _{0 0 1 0 0 0 0 0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0}
MSB
LSB MSB
Data
LSB
SO
HI-Z
Document #: 001-53872 Rev. *E
Page 13 of 36
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