CY8C28243_11 Datasheet, PDF (12/78 Pages) Cypress Semiconductor – PSoC Programmable System-on-Chip

CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
28-Pin Part Pinout
Table 4. 28-Pin Part Pinout (SSOP)
Pin
Type
Pin
No. _{Digital Analog} Name
Description
CY8C28403, CY8C28413, CY8C28433, CY8C28445, and
CY8C28452 28-Pin PSoC Devices
1
I/O
I, M, S P0[7] Analog column mux and SAR ADC
input.^[8]
S, AI, M, P0[7] 1
28
2
I/O I/O, M, S P0[5] Analog column mux and SAR ADC input.
S, AIO, M, P0[5] 2
27
Analog column output.^{[8, 9]}
S, AIO, M, P0[3] 3
26
3
I/O I/O, M, S P0[3] Analog column mux and SAR ADC input.
S, AI, M, P0[1] ₄
25
Analog column output.^{[8, 9]}
M, P2[7] 5
24
4
I/O
I, M, S P0[1] Analog column mux and SAR ADC
input.^[8]
5
I/O
M
P2[7]
6
I/O
7
I/O
8
I/O
M
P2[5]
I, M P2[3] Direct switched capacitor block input.^[12]
I, M P2[1] Direct switched capacitor block input.^[12]
M, P2[5] 6
23
AI, M, P2[3] 7 _SSOP 22
AI, M, P2[1] 8
21
SMP 9
20
I2C0 SCL, M, P1[7] 10
19
I2C0 SDA, M, P1[5] 11
18
M, P1[3] ₁₂
17
9
Output
SMP Switch Mode Pump (SMP) connection to ^{I2C0 SCL, XTALin, M, P1[1] 13}
16
external components.
Vss 14
15
10 I/O
M
P1[7] I2C0 Serial Clock (SCL).
11 I/O
M
P1[5] I2C0 Serial Data (SDA).
12 I/O
M
P1[3]
13 I/O
M
P1[1] Crystal Input (XTALin), I2C0 Serial Clock
(SCL), ISSP-SCLK^[7].
14
Power
15 I/O
M
16 I/O
M
V_SS
P1[0]
P1[2]
Ground connection.
Crystal Output (XTALout), I2C0 Serial
Data (SDA), ISSP-SDATA^[7].
I2C1 Serial Data (SDA).^[10]
17 I/O
18 I/O
M
P1[4] Optional External Clock Input (EXTCLK).
M
P1[6] I2C1 Serial Clock (SCL).^[10]
19
Input
XRES Active high external reset with internal
pull-down.
20 I/O
I, M P2[0] Direct switched capacitor block input.^[13]
21 I/O
I, M P2[2] Direct switched capacitor block input.^[13]
22 I/O
M
P2[4] External Analog Ground (AGND).
23 I/O
M
P2[6] External Voltage Reference (VRef).
24 I/O I, M, S P0[0] Analog column mux and SAR ADC
input.^[8]
25 I/O I/O, M, S P0[2] Analog column mux and SAR ADC input.
Analog column output.^{[8, 11]}
26 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input.
Analog column output.^{[8, 11]}
27 I/O I, M, S P0[6] Analog column mux and SAR ADC
input.^[8]
28
Power
V_DD Supply voltage.
LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input
Vdd
P0[6], M, AI, S
P0[4], M, AIO, S
P0[2], M, AIO, S
P0[0], M, AI, S
P2[6], M, External VRef
P2[4], M, External AGND
P2[2], M, AI
P2[0], M, AI
XRES
P1[6], M, I2C1 SCL
P1[4], M, EXTCLK
P1[2], M, I2C1 SDA
P1[0], M, XTALout, I2C0 SDA
Notes
12. This pin is not a direct switched capacitor block analog input for CY8C28x03 and CY8C28x13 devices.
13. This pin is not a direct switched capacitor block analog input for CY8C28x03, CY8C28x13, CY8C28x23, and CY8C28x33 devices.
Document Number: 001-48111 Rev. *I
Page 12 of 78