CY8C27143_13 Datasheet, PDF (12/64 Pages) Cypress Semiconductor – PSoC® Programmable System-on-Chip™

CY8C27143, CY8C27243
CY8C27443, CY8C27543
CY8C27643
48-pin Part Pinout
Table 6. Pin Definitions – 48-pin Part Pinout (SSOP)
Pin
Type
Pin
No. _{Digital Analog} Name
Description
1
I/O
I
P0[7] Analog column mux input
2
I/O
I/O P0[5] Analog column mux input and column output
3
I/O
I/O P0[3] Analog column mux input and column output
4
I/O
I
P0[1] Analog column mux input
5
I/O
P2[7]
6
I/O
P2[5]
7
I/O
I
P2[3] Direct switched capacitor block input
8
I/O
I
P2[1] Direct switched capacitor block input
9
I/O
P4[7]
10
I/O
P4[5]
11
I/O
P4[3]
12
I/O
P4[1]
13
Power
SMP SMP connection to external components
required
14
I/O
P3[7]
15
I/O
P3[5]
16
I/O
P3[3]
17
I/O
P3[1]
18
I/O
P5[3]
19
I/O
20
I/O
21
I/O
P5[1]
P1[7]
P1[5]
I²C SCL
I²C SDA
22
I/O
23
I/O
P1[3]
P1[1]
CISrSysPt-aSl _CInLpKu[t₆(_]XTALin), I²C SCL,
24
Power
25
I/O
Vss
P1[0]
Ground connection
Crystal output (XTALout), I²C SDA,
ISSP-SDATA.^[6]
26
I/O
P1[2]
27
I/O
P1[4] Optional external clock input (EXTCLK)
28
I/O
P1[6]
29
I/O
P5[0]
30
I/O
P5[2]
31
I/O
P3[0]
32
I/O
P3[2]
33
I/O
P3[4]
34
I/O
P3[6]
35
Input
XRES Active high external reset with internal pull
down
36
I/O
P4[0]
37
I/O
P4[2]
38
I/O
P4[4]
39
I/O
P4[6]
40
I/O
I
P2[0] Direct switched capacitor block input
41
I/O
I
P2[2] Direct switched capacitor block input
42
I/O
P2[4] External analog ground (AGND)
43
I/O
P2[6] External voltage reference (VRef)
44
I/O
I
P0[0] Analog column mux input
45
I/O
I/O P0[2] Analog column mux input and column output
46
I/O
I/O P0[4] Analog column mux input and column output
47
I/O
I
P0[6] Analog column mux input
48
Power
V_DD Supply voltage
LEGEND: A = Analog, I = Input, and O = Output.
Figure 7. CY8C27643 48-pin PSoC Device
A, I, P0[7] 1
A, IO, P0[5] 2
A, IO, P0[3] ₃
A, I, P0[1] 4
P2[7] 5
P2[5] 6
A, I, P2[3] 7
A, I, P2[1] 8
P4[7] 9
P4[5] 10
P4[3] 11
P4[1] 12
SMP 13
P3[7] 14
P3[5] 15
P3[3] 16
P3[1] 17
P5[3] 18
P5[1] 19
I2C SCL, P1[7] ₂₀
I2C SDA, P1[5] 21
P1[3] 22
I2C SCL, XTALin, P1[1] 23
V_SS 24
SSOP
48 VDD
47 P0[6], A, I
46 ^{P0[4], A, IO}
45 ^{P0[2], A, IO}
44 ^{P0[0], A, I}
43 P2[6], External VRef
42 ^{P2[4], External AGND}
41 ^{P2[2], A, I}
40 ^{P2[0], A, I}
39 P4[6]
38 P4[4]
37 P4[2]
36 P4[0]
35 ^XRES
34 P3[6]
33 ^P3[4]
32 ^P3[2]
31 ^P3[0]
30 ^P5[2]
29 P5[0]
28 ^P1[6]
27 ^{P1[4], EXTCLK}
26 ^P1[2]
25 ^{P1[0], XTALout, I2C SDA}
Note
6. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12012 Rev. *X
Page 12 of 64