CY8C20534 Datasheet, PDF (12/34 Pages) Cypress Semiconductor – PSoC® Mixed-Signal Array

CY8C20534, CY8C20434
CY8C20334, CY8C20234
Table 5. 48-Pin OCD Part Pinout (QFN ^[2]) (continued)
Pin No.
Digital
Analog
Name
Description
11
IO
I
P0[1]
12
NC
No connection.
13
NC
No connection.
14
NC
No connection.
15
NC
No connection.
16
IOH
I
17
IOH
I
P1[3]
P1[1]
SPI CLK.
CLK^[1], I²C SCL, SPI MOSI.
18
Power
Vss
Ground connection.
19
CCLK
OCD CPU clock output.
20
21
IOH
I
HCLK
P1[0]
OCD high speed clock output.
DATA^[1], I²C SDA.
22
IOH
I
P1[2]
23
NC
No connection.
24
NC
No connection.
25
NC
No connection.
26
IOH
I
P1[4]
Optional external clock input (EXTCLK).
27
IOH
I
P1[6]
28
Input
XRES
Active high external reset with internal pull down.
29
IO
I
P3[0]
30
IO
I
P3[2]
31
IO
I
P2[0]
32
IO
I
P2[2]
33
IO
I
P2[4]
34
IO
I
P2[6]
35
IO
I
P0[0]
36
IO
I
P0[2]
37
NC
No connection.
38
NC
No connection.
39
NC
No connection.
40
IO
I
P0[6]
Analog bypass.
41
Power
Vdd
Supply voltage.
42
OCDO
OCD odd data output.
43
OCDE
OCD even data IO.
44
IO
I
P0[7]
45
IO
I
P0[5]
46
IO
I
P0[3]
Integrating input.
47
Power
Vss
Ground connection.
48
NC
No connection.
CP
Power
Vss
Center pad is connected to ground.
A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive.
Document Number: 001-05356 Rev. *D
Page 12 of 34
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