CY7C924ADX_07 Datasheet, PDF (12/58 Pages) Cypress Semiconductor – 200 MBaud HOTLink® Transceiver

CY7C924ADX
Pin Descriptions (continued)
CY7C924ADX HOTLink Transceiver
Pin
Number
Name
3
LFI*
Power
80, 87, V_DDA
88, 95,
96, 98
76, 79,
83, 84,
91, 92,
99
V_SSA
14, 17, V_DD
35, 55,
62, 64
11, 13, V_SS
15, 26,
37, 38,
39, 57,
63, 66
I/O Characteristics
Signal Description
TTL output, changes Link Fault Indication Output. Active LOW. LFI* changes synchronous with
following RXCLK↑ RXCLK. This output is driven LOW when the serial link currently selected by
A/B* is not suitable for data recovery. This can be caused by
• Serial Data Amplitude below acceptable levels.
• Input transition density not sufficient for PLL clock recovery.
• Serial Data stream outside an acceptable frequency range of operation.
• CARDET LOW.
Power for PECL-compatible I/O signals and internal analog circuits.
Ground for PECL-compatible I/O signals and internal analog circuits.
Power for CMOS I/O signals and internal logic circuits.
Ground for CMOS I/O signals and internal logic circuits.
CY7C924ADX HOTLink Operation
Overview
The CY7C924ADX is designed to move parallel data across
both short and long distances with minimal overhead or host
system intervention. To accomplish this it converts the parallel
characters into a serial bit stream, transmits these serial bits
at high speed, and converts the received serial bits back into
the original parallel data format.
The CY7C924ADX offers a large feature set, so it can be used
in a wide range of host systems. Some of the configuration
options are:
• 8 bit, 10 bit or 12 bit character size
• User definable data packet or frame structure
• Two octave data rate range
• Asynchronous (FIFOed) or synchronous data interface
• 8B/10B encoded or nonencoded (raw data)
• Embedded or bypassable FIFO data storage
• Multi-PHY capability
• Point-to-point, point-to-multipoint, or ring data transport
This flexibility allows the CY7C924ADX to meet the data
transport needs of almost any system.
Transmit Data Path
Transmit Data Interface/Transmit Data FIFO
The transmit data interface to the host system is configurable
as either an asynchronous buffered (FIFOed) parallel interface
or as a synchronous pipeline register. The bus itself can be
configured for operation with 8 bit, 10 bit or 12 bit data.
When configured for asynchronous operation (where the
host-bus interface clock operates asynchronous to the serial
character and bit stream clocks), the host interface becomes
that of a synchronous FIFO clocked by TXCLK. In these
configurations an internal 256 character Transmit FIFO is
enabled. It allows the host interface to be written at any rate
from DC to 50 MHz.
When configured for synchronous operation, the transmit
interface is clocked by REFCLK and operates synchronous to
the internal character and bit stream clocks. The input register
must be written at the character rate, but REFCLK can operate
at one, two or four times the character rate.
Both asynchronous and synchronous interface operations
support two interface timing models: UTOPIA and Cascade.
The UTOPIA timing model is designed to match the active
levels, bus timing, and signal sequencing called out in the ATM
Forum UTOPIA specification. The Cascade timing model is
designed to match a host bus that resembles a synchronous
FIFO. These timing models allow the CY7C924ADX to directly
couple to host systems, registers, state machines, FIFOs, and
so on, with minimal and in many cases no external glue logic.
Document #: 38-02008 Rev. *E
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