CY7C64215_08 Datasheet, PDF (12/30 Pages) Cypress Semiconductor – enCoRe™ III Full Speed USB Controller

CY7C64215
Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
Addr
(1,Hex)
Access
00
RW
Name
PMA0_WA
Addr
(1,Hex)
40
Access
RW
PRT0DM1
01
RW
PMA1_WA
41
RW
PRT0IC0
02
RW
PMA2_WA
42
RW
PRT0IC1
03
RW
PMA3_WA
43
RW
PRT1DM0
04
RW
PMA4_WA
44
RW
PRT1DM1
05
RW
PMA5_WA
45
RW
PRT1IC0
06
RW
PMA6_WA
46
RW
PRT1IC1
07
RW
PMA7_WA
47
RW
PRT2DM0
08
RW
48
PRT2DM1
09
RW
49
PRT2IC0
0A
RW
4A
PRT2IC1
0B
RW
4B
PRT3DM0
0C
RW
4C
PRT3DM1
0D
RW
4D
PRT3IC0
0E
RW
4E
PRT3IC1
0F
RW
4F
PRT4DM0
10
RW
PMA0_RA
50
RW
PRT4DM1
11
RW
PMA1_RA
51
RW
PRT4IC0
12
RW
PMA2_RA
52
RW
PRT4IC1
13
RW
PMA3_RA
53
RW
PRT5DM0
14
RW
PMA4_RA
54
RW
PRT5DM1
15
RW
PMA5_RA
55
RW
PRT5IC0
16
RW
PMA6_RA
56
RW
PRT5IC1
17
RW
PMA7_RA
57
RW
18
58
19
59
1A
5A
1B
5B
PRT7DM0
1C
RW
5C
PRT7DM1
1D
RW
5D
PRT7IC0
1E
RW
5E
PRT7IC1
1F
RW
5F
DBB00FN
20
RW
CLK_CR0
60
RW
DBB00IN
21
RW
CLK_CR1
61
RW
DBB00OU
22
RW
ABF_CR0
62
RW
23
AMD_CR0
63
RW
DBB01FN
24
RW
CMP_GO_EN
64
RW
DBB01IN
25
RW
65
RW
DBB01OU
26
RW
AMD_CR1
66
RW
27
ALT_CR0
67
RW
DCB02FN
28
RW
68
DCB02IN
29
RW
69
DCB02OU
2A
RW
6A
2B
6B
DCB03FN
2C
RW
TMP_DR0
6C
RW
DCB03IN
2D
RW
TMP_DR1
6D
RW
DCB03OU
2E
RW
TMP_DR2
6E
RW
2F
TMP_DR3
6F
RW
30
ACB00CR3
70
RW
31
ACB00CR0
71
RW
32
ACB00CR1
72
RW
33
ACB00CR2
73
RW
34
ACB01CR3
74
RW
35
ACB01CR0
75
RW
36
ACB01CR1
76
RW
37
ACB01CR2
77
RW
38
78
39
79
3A
7A
3B
7B
3C
7C
3D
7D
3E
7E
3F
7F
Blank fields are Reserved and should not be accessed.
Name
ASC10CR0
Addr
(1,Hex)
80
ASC10CR1
81
ASC10CR2
82
ASC10CR3
83
ASD11CR0
84
ASD11CR1
85
ASD11CR2
86
ASD11CR3
87
88
89
8A
8B
8C
8D
8E
8F
90
ASD20CR1
91
ASD20CR2
92
ASD20CR3
93
ASC21CR0
94
ASC21CR1
95
ASC21CR2
96
ASC21CR3
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
USBIO_CR2
USB_CR1
EP1_CR0
EP2_CR0
EP3_CR0
EP4_CR0
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
IMO_TR
ILO_TR
BDG_TR
ECO_TR
MUX_CR4
MUX_CR5
CPU_F
DAC_CR
CPU_SCR1
CPU_SCR0
Addr
(1,Hex)
C0
C1
Access
RW
#
C4
#
C5
#
C6
#
C7
#
C8
C9
CA
CB
CC
CD
CE
CF
D0
RW
D1
RW
D2
RW
D3
RW
D4
D5
D6
D7
D8
RW
D9
RW
DA
RW
DB
RW
DC
DD
RW
DE
RW
DF
RW
E0
RW
E1
RW
E2
RW
E3
RW
E4
R
E5
E6
E7
E8
W
E9
W
EA
RW
EB
W
EC
RW
ED
RW
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
RL
F8
F9
FA
FB
FC
FD
RW
FE
#
FF
#
Document 38-08036 Rev. *B
Page 12 of 30
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