CY7C601XX_09 Datasheet, PDF (12/68 Pages) Cypress Semiconductor – enCoRe II Low Voltage Microcontroller

CY7C601xx, CY7C602xx
9.2.9 Source Indirect Post Increment
The result of an instruction using this addressing mode is placed
in the Accumulator. Operand 1 is an address pointing to a
location within the memory space, which contains an address
(the indirect address) for the source of the instruction. The
indirect address is incremented as part of the instruction
execution. This addressing mode is only valid on the MVI
instruction. The instruction using this addressing mode is two
bytes in length. Refer to the PSoC Designer: Assembly
Language User Guide for further details on MVI instruction.
Table 9-15. Source Indirect Post Increment
Opcode
Instruction
Operand 1
Source Address Address
Example
MVI A, [8] ;In this case, the value in the memory location
at address 8 is an indirect address. The
memory location pointed to by the Indirect
address is moved into the Accumulator. The
indirect address is then incremented.
9.2.10 Destination Indirect Post Increment
The result of an instruction using this addressing mode is placed
within the memory space. Operand 1 is an address pointing to a
location within the memory space, which contains an address
(the indirect address) for the destination of the instruction. The
indirect address is incremented as part of the instruction
execution. The source for the instruction is the Accumulator. This
addressing mode is only valid on the MVI instruction. The
instruction using this addressing mode is two bytes in length.
Table 9-16. Destination Indirect Post Increment
Opcode
Instruction
Operand 1
Destination Address Address
Example
MVI [8], A
;In this case, the value in the memory
location at address 8 is an
indirect;address. The Accumulator is
moved into the memory location pointed
to by the indirect address. The indirect
address is then incremented.
10. Instruction Set Summary
The instruction set is summarized in Table 10-1 numerically and serves as a quick reference. For more information, the Instruction
Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (available on the www.cypress.com
web site).
Table 10-1. Instruction Set Summary Sorted Numerically by Opcode Order
Instruction Format^{[1, 2]} Flags
Instruction Format Flags
Instruction Format Flags
00 15 1 SSC
01 4 2 ADD A, expr
C, Z
02 6 2 ADD A, [expr]
C, Z
03 7 2 ADD A, [X+expr]
C, Z
04 7 2 ADD [expr], A
C, Z
05 8 2 ADD [X+expr], A
C, Z
06 9 3 ADD [expr], expr
C, Z
07 10 3 ADD [X+expr], expr C, Z
08 4 1 PUSH A
09 4 2 ADC A, expr
C, Z
0A 6 2 ADC A, [expr]
C, Z
0B 7 2 ADC A, [X+expr]
C, Z
0C 7 2 ADC [expr], A
C, Z
0D 8 2 ADC [X+expr], A
C, Z
0E 9 3 ADC [expr], expr
C, Z
0F 10 3 ADC [X+expr], expr C, Z
10 4 1 PUSH X
11 4 2 SUB A, expr
C, Z
12 6 2 SUB A, [expr]
C, Z
2D 8 2 OR [X+expr], A
Z
2E 9 3 OR [expr], expr
Z
2F 10 3 OR [X+expr], expr Z
30 9 1 HALT
31 4 2 XOR A, expr
Z
32 6 2 XOR A, [expr]
Z
33 7 2 XOR A, [X+expr]
Z
34 7 2 XOR [expr], A
Z
35 8 2 XOR [X+expr], A
Z
36 9 3 XOR [expr], expr
Z
37 10 3
38 5 2
39 5 2
3A 7 2
3B 8 2
3C 8 3
3D 9 3
3E 10 2
3F 10 2
XOR [X+expr], expr
ADD SP, expr
CMP A, expr
CMP A, [expr]
CMP A, [X+expr]
CMP [expr], expr
CMP [X+expr], expr
MVI A, [ [expr]++ ]
MVI [ [expr]++ ], A
Z
if (A=B)
Z=1
if (A<B)
C=1
Z
5A 5 2
5B 4 1
5C 4 1
5D 6 2
5E 7 2
5F 10 3
60 5 2
61 6 2
62 8 3
63 9 3
64 4 1
65 7 2
66 8 2
67 4 1
68 7 2
69 8 2
6A 4 1
6B 7 2
6C 8 2
MOV [expr], X
MOV A, X
Z
MOV X, A
MOV A, reg[expr] Z
MOV A, reg[X+expr] Z
MOV [expr], [expr]
MOV reg[expr], A
MOV reg[X+expr], A
MOV reg[expr], expr
MOV reg[X+expr],
expr
ASL A
C, Z
ASL [expr]
C, Z
ASL [X+expr]
C, Z
ASR A
C, Z
ASR [expr]
C, Z
ASR [X+expr]
C, Z
RLC A
C, Z
RLC [expr]
C, Z
RLC [X+expr]
C, Z
Document 38-16016 Rev. *E
Page 12 of 68
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