CY7C4261V Datasheet, PDF(12/16 Page) Cypress Semiconductor – 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

CY7C4261V Datasheet, PDF (12/16 Pages) Cypress Semiconductor – 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs

◁

Switching Waveforms (continued)

Full Flag Timing

NO WRITE

WCLK

D0 âD8

tSKEW1 [12]

tWFF

WEN1

WEN2

(if applicable)

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

NO WRITE

tDS

tSKEW1 [12]

DATA WRITE

tWFF

DATA WRITE

RCLK

REN1,

REN2

tENS

tENH

tENS

tENH

Q0 âQ8

LOW

DATA IN OUTPUT REGISTER

DATA READ

NEXT DATA READ

Programmable Almost Empty Flag Timing

tCLKH

tCLKL

WCLK

WEN1

tENS tENH

WEN2

(if applicable)

PAE

RCLK

tENS tENH

Note 20

tSKEW2 [19]

tPAE

N + 1 WORDS

IN FIFO

Note21

tPAE

REN1,

REN2

tENS

tENS tENH

Notes:

19. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising

RCLK is less than tSKEW2, then PAE may not change state until the next RCLK.

20. PAE offset = n.

21. If a read is performed on this rising edge of the read clock, there will be Empty + (nâ1) words in the FIFO when PAE goes LOW.

Document #: 38-06013 Rev. *A

Page 12 of 16

▷