CY7C343 Datasheet, PDF (12/19 Pages) Cypress Semiconductor – 64-Macrocell MAX EPLD

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Internal Switching Characteristics Over Operating Range (continued)^[7]
Parameter
t_FD
t_PRE
t_CLR
t_PCW
t_PCR
t_PIA
Description
Feedback Delay
Com’l/Ind
Mil
Asynchronous Register Preset Time
Com’l/Ind
Mil
Asynchronous Register Clear Time
Com’l/Ind
Mil
Asynchronous Preset and Clear Pulse Width Com’l /Ind
Mil
Asynchronous Preset and Clear Recovery Com’l/Ind
Time
Mil
Programmable Interconnect Array Delay Time Com’l/Ind
Mil
7C343-20
Min. Max.
1
1
4
4
4
4
4
4
4
4
12
12
Internal Switching Characteristics Over Operating Range ^[7]
Parameter
t_IN
t_IO
t_EXP
t_LAD
t_LAC
t_OD
t_ZX
t_XZ
t_RSU
t_RH
t_LATCH
t_RD
t_COMB
Description
Dedicated Input Pad and Buffer Delay
Com’l/Ind
Mil
I/O Input Pad and Buffer Delay
Com’l/Ind
Mil
Expander Array Delay
Com’l/Ind
Mil
Logic Array Data Delay
Com’l/Ind
Mil
Logic Array Control Delay
Com’l/Ind
Mil
Output Buffer and Pad Delay
Com’l/Ind
Output Buffer Enable Delay^[28]
Mil
Com’l/Ind
Mil
Output Buffer Disable Delay
Com’l/Ind
Mil
Register Set-Up Time Relative to Clock Signal Com’l/Ind
at Register
Mil
Register Hold Time Relative to Clock Signal at Com’l/Ind
Register
Mil
Flow-Through Latch Delay
Com’l/Ind
Mil
Register Delay
Com’l/Ind
Transparent Mode Delay^[29]
Mil
Com’l/Ind
Mil
7C343-30
Min. Max.
7
7
5
5
14
14
14
14
12
12
5
5
11
11
11
11
8
8
8
8
4
4
2
2
4
4
CY7C343
7C343-25
Min. Max. Unit
1
ns
1
5
ns
5
5
ns
5
5
ns
5
5
ns
5
14
ns
14
7C343-35
Min. Max. Unit
9
ns
9
7
ns
7
20
ns
20
16
ns
16
13
ns
13
6
ns
6
13
ns
13
13
ns
13
10
ns
10
12
ns
12
4
ns
4
2
ns
2
4
ns
4
Document #: 38-03015 Rev. *B
Page 12 of 19