CY7C1392AV18 Datasheet, PDF (12/21 Pages) Cypress Semiconductor – 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

PRELIMINARY
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
Switching Waveforms^{[21, 22, 23]}
NOP
READ
READ
WRITE
WRITE
READ
NOP
(burst of 2) (burst of 2) (burst of 2) (burst of 2) (burst of 2)
1
2
3
4
5
6
7
8
K
tKH tKL
tCYC
tKHKH
K#
LD#
tSC _tHC
R/W #
A
D
A0
A1
tSA tHA
A2
A3
A4
tHD
tHD
tSD
tSD
D20 D21 D30 D31
Q Qx2
tKHCH
C
C#
CQ
CQ#
tKHCH
tCO
tCLZ
Q00 Q01 Q10 Q11
tCO
tDOH
tCLZ
tDOH
Q40 Q41
tCQD
tCCQO
tCQOH
tCCQO
tCQOH
tKH tKL
tCYC
tKHKH
DON’T CARE
UNDEFINED
Notes:
21. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
22. Output are disabled (High-Z) one clock cycle after a NOP.
23. In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram
Document #: 38-05503 Rev. *A
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