CY7C1241V18 Datasheet, PDF (12/28 Pages) Cypress Semiconductor – 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

CY7C1241V18
CY7C1256V18
CY7C1243V18
CY7C1245V18
Write Cycle Descriptions
The write cycle description table for CY7C1245V18 follows.^{[2, 10]}
BWS₀ BWS₁ BWS₂ BWS₃ K K
Comments
L
L
L
L L–H – During the data portion of a write sequence, all four bytes (D_[35:0]) are written
into the device.
L
L
L
L
– L–H During the data portion of a write sequence, all four bytes (D_[35:0]) are written
into the device.
L
H
H
H L–H – During the data portion of a write sequence, only the lower byte (D_[8:0]) is
written into the device. D_[35:9] remains unaltered.
L
H
H
H
– L–H During the data portion of a write sequence, only the lower byte (D_[8:0]) is
written into the device. D_[35:9] remains unaltered.
H
L
H
H L–H – During the data portion of a write sequence, only the byte (D_[17:9]) is written
into the device. D_[8:0] and D_[35:18] remain unaltered.
H
L
H
H
– L–H During the data portion of a write sequence, only the byte (D_[17:9]) is written
into the device. D_[8:0] and D_[35:18] remain unaltered.
H
H
L
H L–H – During the data portion of a write sequence, only the byte (D_[26:18]) is written
into the device. D_[17:0] and D_[35:27] remain unaltered.
H
H
L
H
– L–H During the data portion of a write sequence, only the byte (D_[26:18]) is written
into the device. D_[17:0] and D_[35:27] remain unaltered.
H
H
H
L L–H – During the data portion of a write sequence, only the byte (D_[35:27]) is written
into the device. D_[26:0] remains unaltered.
H
H
H
L
– L–H During the data portion of a write sequence, only the byte (D_[35:27]) is written
into the device. D_[26:0] remains unaltered.
H
H
H
H L–H – No data is written into the device during this portion of a write operation.
H
H
H
H
– L–H No data is written into the device during this portion of a write operation.
Document Number: 001-06365 Rev. *C
Page 12 of 28
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