CY7C024AV_09 Datasheet, PDF (12/19 Pages) Cypress Semiconductor – 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM

CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
ADDRESS
Figure 8. Write Cycle No. 1: R/W Controlled Timing^{[34, 35, 36, 37]}
t_WC
OE
[38, 39]
CE
R/W
DATA OUT
DATA IN
t_AW
t_SA
t_PWE^[37]
NOTE 41
t_HZWE^[40]
t_SD
t_HA
t_LZWE
t_HD
ADDRESS
[38, 39]
CE
R/W
DATA IN
Figure 9. Write Cycle No. 2: CE Controlled Timing^{[34, 35, 36, 42]}
t_WC
t_AW
t_SA
t_SCE
t_HA
t_SD
t_HD
t_HZOE^[40]
NOTE 41
Notes
34. R/W or CE must be HIGH during all address transitions.
35. A write occurs during the overlap (t_SCE or t_PWE) of a LOW CE or SEM and a LOW UB or LB.
36. t_HA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
37. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t_PWE or (t_HZWE + t_SD) to enable the IO drivers to turn off and
data to be placed on the bus for the required t_SD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified t_PWE.
38. To access RAM, CE = V_IL, SEM = V_IH.
39. To access upper byte, CE = V_IL, UB = V_IL, SEM = V_IH.
To access lower byte, CE = V_IL, LB = V_IL, SEM = V_IH.
40. Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100 percent tested.
41. During this period, the IO pins are in the output state, and input signals must not be applied.
42. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
Document #: 38-06052 Rev. *J
Page 12 of 19
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