CY28347 Datasheet, PDF (12/22 Pages) Cypress Semiconductor – Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems

CY28347
AC Parameters (continued)
66 MHz
100 MHz
133 MHz
200 MHz
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
REF
TDC
REF Duty Cycle
45
55
45
55
45
55
45
55 % 5,10,6
TPeriod REF Period
69.8413 71.0 69.8413 71.0 69.8413 71.0 69.8413 71.0 ns 5,6,10
Tr/Tf
REF Rise and Fall Times 1.0 4.0 1.0 4.0 1.0 4.0 1.0 4.0 ns 10,21
TCCJ REF Cycle-to-Cycle Jitter
1000
1000
1000
1000 ps 6,10,11,12
DDR
VX
Crossing Point Voltage of 0.5*VD 0.5*VD 0.5*VD 0.5*VD 0.5*VD 0.5*VD 0.5*VD 0.5*VD V 23
DDRT/C
DD–0.2 DD+0.2 DD–0.2 DD+0.2 DD–0.2 DD+0.2 DD–0.2 DD+0.2
VD
Differential Voltage Swing 0.7 VDDD + 0.7 VDDD + 0.7 VDDD + 0.7 VDDD + V 22
0.6
0.6
0.6
0.6
TDC
DDRT/C(0:5) Duty Cycle 45
55
45
55
45
55
45
55 % 14
TPeriod DDRT/C(0:5) Period
14.85 15.3 9.85 10.2 14.85 15.3 9.85 10.2 ns 14
Tr/Tf
DDRT/C(0:5) Rise/Fall
1
3
1
3
1
3
1
3 V/ns 21
Slew Rate
TSKEW DDRT/C to Any DDRT/C
100
100
100
100 ps 10,11,14
Clock Skew
TCCJ
DDRT/C(0:5)
Cycle-to-Cycle Jitter
±75
±75
±75
±75 ps 10,11,14
THPJ
DDRT/C(0:5) Half Period
Jitter
±100
±100
±100
±100 ps 10,11,14
TDelay BUF_IN to Any DDRT/C 1
4
1
4
1
4
1
4 ns 6,10
Delay
TSKEW FBOUT to Any DDRT/C
100
100
100
100 ps 6,10
Skew
tstable
All Clock Stabilization
from Power-up
1.5
1.5
1.5
1.5 ms 12
Connection Circuit DDRT/C Signals
DDRT
T_PCB
Measurement Point
16 pF
100Ω
DDRC
T_PCB
Measurement Point
16 pF
Figure 1. Differential DDR Termination
Document #: 38-07352 Rev. *C
Page 12 of 22