CY14E102L Datasheet, PDF (12/21 Pages) Cypress Semiconductor – 2-Mbit (256K x 8/128K x 16) nvSRAM

ADVANCE
CY14E102L, CY14E102N
Switching Waveforms (continued)
Figure 7. SRAM Write Cycle #1: WE Controlled^{[13, 21, 22, 23]}
ADDRESS
CE
WE
tSA
tWC
tSCE
tAW
tPWE
tHA
BHE , BLE
DATA IN
DATA OUT
tBW
PREVIOUS DATA
tHZWE
tSD
DATA VALID
HIGH IMPEDANCE
tHD
tLZWE
ADDRESS
CE
WE
BHE , BLE
DATA IN
DATA OUT
Figure 8. SRAM Write Cycle #2: CE Controlled^{[13, 21, 22, 23]}
t_WC
t_SA
t_SCE
t_AW
t_HA
t_PWE
t_BW
t_SD
t_HD
DATA VALID
HIGH IMPEDANCE
Document Number: 001-45755 Rev. *A
Page 12 of 21
[+] Feedback