CYNCP80192 Datasheet, PDF (11/42 Pages) Cypress Semiconductor – Network Database Coprocessor

CYNCP80192
5.0 Clocks
The CYNPC80192 receives up to a 100-MHz master CLK at the coprocessor interface. The CYNPC80192 then generates the
CLK2X and a phase signal PHS_L for the NSEs, and the SCLK for the associative data SSRAMs, as shown in Figure 5-1.
Input CLK to CLK
CYNPC80192
Input signals CLK2X
for NSEs
PHS_L
CLK for SSRAMs SCLK
Figure 5-1. NDC Clocks
Document #: 38-02043 Rev. *B
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