CY8C20134_12 Datasheet, PDF (11/48 Pages) Cypress Semiconductor – PSoC® Programmable System-on-Chip™

CY8C20134, CY8C20234, CY8C20334
CY8C20434, CY8C20534, CY8C20634
Table 4. Pin Definitions – CY8C20000 48-Pin OCD (QFN) ^[3]
Pin No.
Digital
Analog
Name
Description
19
CCLK
OCD high speed clock output
20
HCLK
DATA^[5], I²C SDA
21
I_OH
I
22
I_OH
I
23
P1[0]
P1[2]
NC
No connection
No connection
24
NC
No connection
25
NC
Optional external clock input (EXTCLK)
26
I_OH
I
27
I_OH
I
28
Input
P1[4]
P1[6]
XRES
Active high external reset with internal pull-down
29
I/O
I
P3[0]
30
I/O
I
31
I/O
I
P3[2]
P2[0]
32
I/O
I
P2[2]
33
I/O
I
P2[4]
34
I/O
I
P2[6]
35
I/O
I
36
I/O
I
P0[0]
P0[2]
37
NC
No connection
38
NC
No connection
39
40
I/O
I
NC
P0[6]
No connection
Analog bypass
41
Power
42
V_DD
OCDO
Supply voltage
OCD odd data output
43
44
I/O
I
45
I/O
I
OCDE
P0[7]
P0[5]
OCD even data I/O
46
I/O
I
P0[3]
Integrating Input
47
Power
48
V_SS
Ground connection
NC
No connection
CP
Power
V_SS
Center pad is connected to ground
A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive.
Note
5. These are the ISSP pins, that are not High Z at POR (Power-on-Reset). See the PSoC Technical Reference Manual for details.
Document Number: 001-05356 Rev. *Q
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