CY7C1643KV18 Datasheet, PDF (11/31 Pages) Cypress Semiconductor – 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)

CY7C1643KV18, CY7C1645KV18
Write Cycle Descriptions
The write cycle description table for CY7C1645KV18 follows. ^{[13, 14]}
BWS₀ BWS₁ BWS₂ BWS₃ K
L
L
L
L L–H
K
Comments
– During the data portion of a write sequence, all four bytes (D_[35:0]) are written into
the device.
L
L
L
L
– L–H During the data portion of a write sequence, all four bytes (D_[35:0]) are written into
the device.
L
H
H
H L–H – During the data portion of a write sequence, only the lower byte (D_[8:0]) is written
into the device. D_[35:9] remains unaltered.
L
H
H
H
– L–H During the data portion of a write sequence, only the lower byte (D_[8:0]) is written
into the device. D_[35:9] remains unaltered.
H
L
H
H L–H – During the data portion of a write sequence, only the byte (D_[17:9]) is written into the
device. D_[8:0] and D_[35:18] remains unaltered.
H
L
H
H
– L–H During the data portion of a write sequence, only the byte (D_[17:9]) is written into the
device. D_[8:0] and D_[35:18] remains unaltered.
H
H
L
H L–H – During the data portion of a write sequence, only the byte (D_[26:18]) is written into
the device. D_[17:0] and D_[35:27] remains unaltered.
H
H
L
H
– L–H During the data portion of a write sequence, only the byte (D_[26:18]) is written into
the device. D_[17:0] and D_[35:27] remains unaltered.
H
H
H
L L–H – During the data portion of a write sequence, only the byte (D_[35:27]) is written into
the device. D_[26:0] remains unaltered.
H
H
H
L
– L–H During the data portion of a write sequence, only the byte (D_[35:27]) is written into
the device. D_[26:0] remains unaltered.
H
H
H
H L–H – No data is written into the device during this portion of a write operation.
H
H
H
H
– L–H No data is written into the device during this portion of a write operation.
Notes
13. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
14.
Is
of
based on a write
a write cycle, as
cycle that was initiated
long as the setup and
in accordance with
hold requirements
the
are
Write Cycle
achieved.
Descriptions
table.
BWS₀,
BWS₁,
BWS₂,
and
BWS₃
can
be
altered
on
different
portions
Document Number: 001-44059 Rev. *I
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