CY7C1348G Datasheet, PDF (11/16 Pages) Cypress Semiconductor – 4-Mbit (128K x 36) Pipelined DCD Sync SRAM

CY7C1348G
Switching Waveforms
Read Timing^[17]
tCYC
CLK
ADSP
ADSC
ADDRESS
GW, BWE,BW
[A:D]
CE
ADV
OE
Data Out (Q)
tCH tCL
tADS tADH
tADS tADH
tAS tAH
A1
A2
tWES tWEH
tCES tCEH
A3
Burst continued with
new base address
Deselect
cycle
tADVS tADVH
ADV suspends burst
t
CLZ
High-Z
tCO
tOEHZ
Q(A1)
tOEV
tCO
tOELZ
tDOH
Q(A2) Q(A2 + 1)
Single READ
tCHZ
Q(A2 + 2)
Q(A2 + 3)
BURST READ
Q(A2) Q(A2 + 1) Q(A3)
Burst wraps around
to its initial state
DON’T CARE
UNDEFINED
Note:
17. On this diagram, when CE is LOW: CE₁ is LOW, CE₂ is HIGH and CE₃ is LOW. When CE is HIGH: CE₁ is HIGH or CE₂ is LOW or CE₃ is HIGH.
Document #: 38-05608 Rev. *D
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