CY7C1330AV25 Datasheet, PDF (11/19 Pages) Cypress Semiconductor – 18-Mbit (512K x 36/1Mbit x 18) Pipelined Register-Register Late Write

PRELIMINARY
CY7C1330AV25
CY7C1332AV25
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan
Instruction Codes
Instruction
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Bit Size—CY7C1330AV25
3
1
32
70
Bit Size—CY7C1332AV25
3
1
32
51
Code
000
001
010
011
100
101
110
111
Description
Captures the Input/Output ring contents.
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operation.
Boundary Scan Order (1 Mbit x 18)
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Bump ID
5R
6T
4P
6R
5T
7T
7P
6N
6L
7K
5L
4L
4K
4F
6H
7G
6F
Bit #
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Bump ID
7E
6D
6A
6C
5C
5A
6B
5B
3B
2B
3A
3C
2C
2A
1D
2E
2G
Bit #
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Bump ID
1H
3G
4D
4E
4G
4H
4M
2K
1L
2M
1N
2P
3T
2R
4N
2T
3R
Document No: 001-07844 Rev. *A
Page 11 of 19
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