CY7C1303BV25_12 Datasheet, PDF (11/25 Pages) Cypress Semiconductor – 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture

CY7C1303BV25
TAP Controller State Diagram
The state diagram for the TAP controller follows. ^[9]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/ ¹
IDLE
SELECT
1
DR-SCAN
0
1
CAPTURE-DR
0
SHIFT-DR
0
1
1
EXIT1-DR
0
PAUSE-DR
0
1
0
EXIT2-DR
1
UPDATE-DR
1
0
1
SELECT
IR-SCAN
0
1
CAPTURE-DR
0
SHIFT-IR
0
1
EXIT1-IR
1
0
PAUSE-IR
0
1
0
EXIT2-IR
1
UPDATE-IR
1
0
Note
9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 38-05627 Rev. *F
Page 11 of 25