CY7C1161V18 Datasheet, PDF (11/29 Pages) Cypress Semiconductor – 18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
Write Cycle Descriptions
The write cycle descriptions of CY7C1161V18 and CY7C1163V18 follow.^{[3, 11]}
BWS₀/ BWS₁/ _K
K
NWS₀ NWS₁
Comments
L
L L–H – During the data portion of a write sequence:
CY7C1161V18 − both nibbles (D_[7:0]) are written into the device.
CY7C1163V18 − both bytes (D_[17:0]) are written into the device.
L
L
– L-H During the data portion of a write sequence:
CY7C1161V18 − both nibbles (D_[7:0]) are written into the device.
CY7C1163V18 − both bytes (D_[17:0]) are written into the device.
L
H L–H – During the data portion of a write sequence:
CY7C1161V18 − only the lower nibble (D_[3:0]) is written into the device, D_[7:4] remains unaltered.
CY7C1163V18 − only the lower byte (D_[8:0]) is written into the device, D_[17:9] remains unaltered.
L
H
– L–H During the data portion of a write sequence:
CY7C1161V18 − only the lower nibble (D_[3:0]) is written into the device, D_[7:4] remains unaltered.
CY7C1163V18 − only the lower byte (D_[8:0]) is written into the device, D_[17:9] remains unaltered.
H
L L–H – During the data portion of a write sequence:
CY7C1161V18 − only the upper nibble (D_[7:4]) is written into the device, D_[3:0] remains unaltered.
CY7C1163V18 − only the upper byte (D_[17:9]) is written into the device, D_[8:0] remains unaltered.
H
L
– L–H During the data portion of a write sequence:
CY7C1161V18 − only the upper nibble (D_[7:4]) is written into the device, D_[3:0] remains unaltered.
CY7C1163V18 − only the upper byte (D_[17:9]) is written into the device, D_[8:0] remains unaltered.
H
H L–H – No data is written into the device during this portion of a write operation.
H
H
– L–H No data is written into the device during this portion of a write operation.
The write cycle operation of CY7C1176V18 follows.^{[3, 11]}
BWS₀ K
L
L–H
L
–
H
L–H
K
– During the data portion of a write sequence, the single byte (D_[8:0]) is written into the device.
L–H During the data portion of a write sequence, the single byte (D_[8:0]) is written into the device.
– No data is written into the device during this portion of a write operation.
H
–
L–H No data is written into the device during this portion of a write operation.
Note
11. Is based upon a Write cycle was initiated per the Write Cycle Description Truth Table. NWS₀, NWS₁, BWS₀, BWS₁, BWS₂, and BWS₃ can be altered on different
portions of a Write cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-06582 Rev. *C
Page 11 of 29
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