CY14C101J_13 Datasheet, PDF (11/31 Pages) Cypress Semiconductor – 1-Mbit (128 K x 8) Serial (I2C) nvSRAM

CY14C101J
CY14B101J
CY14E101J
By Master
SDA Line
By nvSRAM
Figure 11. Single-Byte Write into nvSRAM (except Hs-mode)
S
T
A
R Memory Slave Address
T
Most Signifiant Address Byte
Least Significant Address Byte
S 1 0 1 0 A2 A1 A16 0
A
A
A
By Master
SDA Line
By nvSRAM
Figure 12. Multi-Byte Write into nvSRAM (except Hs-mode)
S
T
A
R _{Memory Slave Address}
T
Most Significant Address
Byte
Least Significant Address
Byte
Data Byte 1
S 1 0 1 0 A2 A1 A16 0
A
A
A
A
Figure 13. Single-Byte Write into nvSRAM (Hs-mode)
By Master
SDA Line
S
T
A
R _{Memory Slave Address}
T
S 1 0 1 0 A2 A1 A16 0
Most Significant Address
Byte
Least Significant Address
Byte
Data Byte 1
By nvSRAM
A
A
A
A
Data Byte
S
T
0
P
P
A
Data Byte N
S
T
0
P
P
A
Data Byte N
S
T
0
P
P
A
Figure 14. Multi-Byte Write into nvSRAM (Hs-mode)
By Master
SDA Line
By nvSRAM
By Master
SDA Line
S
T
A
R _{Hs-mode command}
T
S 0 0 0 01 X X X
Memory Slave Address
Sr 1 0 1 0 A2 A1 A16 0
Most Significant Address
Byte
Least Significant Address
Byte
A
Data Byte 2
A
Data Byte 3
A
A
S
T
Data Byte N
0
P
P
By nvSRAM
A
A
A
Data Byte 1
A
Document Number: 001-54050 Rev. *M
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