CY14B512Q1_13 Datasheet, PDF (11/27 Pages) Cypress Semiconductor – 512-Kbit (64 K x 8) Serial (SPI) nvSRAM

CY14B512Q1
CY14B512Q2
CY14B512Q3
Figure 8. Write Status Register (WRSR) Instruction Timing
CS
SCK
01 23 4 5 6 701 2 3 4 5 6 7
Opcode
Data in
SI
0 0 0 0 0 0 0 1 D7 X X X D3 ^D2 X X
MSB
LSB
SO
HI-Z
Write Protection and Block Protection
CY14B512Q1/CY14B512Q2/CY14B512Q3 provides features
for both software and hardware write protection using WRDI
instruction and WP. Additionally, this device also provides block
protection mechanism through BP0 and BP1 pins of the Status
Register.
The Write Enable and disable status of the device is indicated by
WEN bit of the Status Register. The write instructions (WRSR
and WRITE) and nvSRAM special instruction (STORE,
RECALL, ASENB, and ASDISB) need the write to be enabled
(WEN bit = ‘1’) before they can be issued.
Write Enable (WREN) Instruction
On power-up, the device is always in the Write Disable state. The
following WRITE, WRSR, or nvSRAM special instruction must
therefore be preceded by a Write Enable instruction. If the device
is not Write Enabled (WEN = ‘0’), it ignores the write instructions
and returns to the standby state when CS is brought HIGH. A
new CS falling edge is required to re-initiate serial
communication. The instruction is issued following the falling
edge of CS. When this instruction is used, the WEN bit of Status
Register is set to ‘1’. WEN bit defaults to ‘0’ on power-up.
Note After completion of a write instruction (WRSR or WRITE)
or nvSRAM special instruction (STORE, RECALL, ASENB, and
ASDISB) instruction, WEN bit is cleared to ‘0’. This is done to
provide protection from any inadvertent writes. Therefore,
WREN instruction must be used before a new write instruction is
issued.
Write Disable (WRDI) Instruction
Write Disable instruction disables the write by clearing the WEN
bit to ‘0’ in order to protect the device against inadvertent writes.
This instruction is issued following the falling edge of CS followed
by opcode for WRDI instruction. The WEN bit is cleared on the
rising edge of CS following a WRDI instruction.
Figure 10. WRDI Instruction
CS
SCK
01 234567
SI
00000100
SO
HI-Z
Block Protection
Block protection is provided using the BP0 and BP1 pins of the
Status Register. These bits can be set using WRSR instruction
and probed using the RDSR instruction. The nvSRAM is divided
into four array segments. One-quarter, one-half, or all of the
memory segments can be protected. Any data within the
protected segment is read only. Table 5 shows the function of
block protect bits.
Table 5. Block Write Protect Bits
Figure 9. WREN Instruction
CS
SCK
01 234567
SI
00000110
Level
0
1 (1/4)
2 (1/2)
3 (All)
Status Register
Bits
BP1
BP0
0
0
0
1
1
0
1
1
Array Addresses Protected
None
0xC000–0xFFFF
0x8000–0xFFFF
0x0000–0xFFFF
SO
HI-Z
Document Number: 001-53873 Rev. *I
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