CY7C1422BV18 Datasheet, PDF (10/28 Pages) Cypress Semiconductor – 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

PRELIMINARY
CY7C1422BV18
CY7C1429BV18
CY7C1423BV18
CY7C1424BV18
Write Cycle Descriptions (CY7C1422BV18 and CY7C1423BV18) ^{[2, 8]}
BWS₀/NWS₀ BWS₁/NWS₁ K
K
Comments
L
L
L-H - During the Data portion of a Write sequence:
CY7C1422BV18 − both nibbles (D_[7:0]) are written into the device,
CY7C1423BV18 − both bytes (D_[17:0]) are written into the device.
L
L
- L-H During the Data portion of a Write sequence:
CY7C1422BV18 − both nibbles (D_[7:0]) are written into the device,
CY7C1423BV18 − both bytes (D_[17:0]) are written into the device.
L
H
L-H - During the Data portion of a Write sequence:
CY7C1422BV18 − only the lower nibble (D_[3:0]) is written into the device. D_[7:4]
will remain unaltered,
CY7C1423BV18 − only the lower byte (D_[8:0]) is written into the device. D_[17:9]
will remain unaltered.
L
H
- L-H During the Data portion of a Write sequence:
CY7C1422BV18 − only the lower nibble (D_[3:0]) is written into the device. D_[7:4]
will remain unaltered,
CY7C1423BV18 − only the lower byte (D_[8:0]) is written into the device. D_[17:9]
will remain unaltered.
H
L
L-H – During the Data portion of a Write sequence:
CY7C1422BV18 − only the upper nibble (D_[7:4]) is written into the device. D_[3:0]
will remain unaltered,
CY7C1423BV18 − only the upper byte (D_[17:9]) is written into the device. D_[8:0]
will remain unaltered.
H
L
– L-H During the Data portion of a Write sequence:
CY7C1422BV18 − only the upper nibble (D_[7:4]) is written into the device. D_[3:0]
will remain unaltered,
CY7C1423BV18 − only the upper byte (D_[17:9]) is written into the device. D_[8:0]
will remain unaltered.
H
H
L-H – No data is written into the devices during this portion of a Write operation.
H
H
– L-H No data is written into the devices during this portion of a Write operation.
Note:
8. Assumes a Write cycle was initiated per the Write Cycle Description Truth Table. BWS₀, BWS₁ in the case of CY7C1422BV18 and CY7C1423BV18 and also
BWS₂, BWS₃ in the case of CY7C1424BV18 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
Document Number: 001-07035 Rev. *B
Page 10 of 28
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