CY7C1351F Datasheet, PDF (10/15 Pages) Cypress Semiconductor – 4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

CY7C1351F
Switching Characteristics Over the Operating Range^{[17, 18]}
133 MHz 117 MHz 100 MHz 66 MHz
Parameter
t_POWER
Clock
Description
V_DD(Typical) to the first Access^[13]
Min. Max. Min. Max. Min. Max. Min. Max. Unit
1
1
1
1
ms
t_CYC
t_CH
t_CL
Output Times
Clock Cycle Time
Clock HIGH
Clock LOW
7.5
8.5
10
15
ns
2.5
3.0
4.0
5.0
ns
2.5
3.0
4.0
5.0
ns
t_CDV
t_DOH
t_CLZ
t_CHZ
t_OEV
t_OELZ
t_OEHZ
Set-up Times
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z^{[14, 15, 16]}
Clock to High-Z^{14, 15, 16]}
OE LOW to Output Valid
OE LOW to Output Low-Z^{[14, 15, 16]}
OE HIGH to Output High-Z^{[14, 15, 16]}
6.5
7.5
8.0
11.0 ns
2.0
2.0
2.0
2.0
ns
0
0
0
0
ns
3.5
3.5
3.5
5.0 ns
3.5
3.5
3.5
6.0 ns
0
0
0
0
ns
3.5
3.5
3.5
6.0 ns
t_AS
t_ALS
t_WES
t_CENS
t_DS
t_CES
Hold Times
Address Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
WE, BW_[A:D] Set-Up Before CLK Rise
CEN Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
1.5
2.0
2.0
2.0
ns
1.5
2.0
2.0
2.0
ns
1.5
2.0
2.0
2.0
ns
1.5
2.0
2.0
2.0
ns
1.5
2.0
2.0
2.0
ns
1.5
2.0
2.0
2.0
ns
t_AH
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
t_ALH
ADV/LD Hold after CLK Rise
0.5
0.5
0.5
0.5
ns
t_WEH
WE, BW_[A:D] Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
t_CENH
CEN Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
t_DH
Data Input Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
t_CEH
Chip Enable Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
Shaded areas contain advance information.
Notes:
13. This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above VDD minimum initially before a read or write operation
can be initiated.
14. t_CHZ, t_CLZ,t_OELZ, and t_OEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
15. At any given voltage and temperature, t_OEHZ is less than t_OELZ and t_CHZ is less than t_CLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve Three-state prior to Low-Z under the same system conditions
16. This parameter is sampled and not 100% tested.
17. Timing reference level is 1.5V when V_DDQ =3.3V and is 1.25V when V_DDQ = 2.5V.
18. Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
Document #: 38-05210 Rev. *B
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