CY7C1325G_11 Datasheet, PDF (10/21 Pages) Cypress Semiconductor – 4-Mbit (256 K x 18) Flow through Sync SRAM Synchronous self timed write

CY7C1325G
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature................................. –65 °C to +150 °C
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Supply voltage on V_DD relative to GND ........–0.5 V to +4.6 V
Supply voltage on V_DDQ relative to GND....... –0.5 V to +V_DD
DC voltage applied to outputs
in tristate ............................................–0.5 V to V_DDQ + 0.5 V
DC input voltage .................................. –0.5 V to V_DD + 0.5 V
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, method 3015)
Latch-up current .................................................... > 200 mA
Operating Range
Range
TemAmpebriaetnutre^]
Commercial 0 °C to +70 °C
Industrial –40 °C to +85 °C
V_DD
3.3 V5% /
+ 10%
V_DDQ
2.5 V – 5%
to V_DD
Neutron Soft Error Immunity
Parameter
Description
Test
Conditions
Typ
Max*
Unit
LSBU
Logical
single bit
upsets
25 °C
361 394 FIT/
Mb
LMBU
Logical multi
bit upsets
25 °C
0 0.01 FIT/
Mb
SEL
Single event
85 °C
0 0.1 FIT/
latch up
Dev
*staN_to_istL_icM_aB_l U_2o_, r
SEL
95%
events occurred
confidence limit
during testing; this column represents a
calculation. For more details refer to
Application Note AN 54908 “Accelerated Neutron SER Testing and Calculation
of Terrestrial Failure Rates”
Electrical Characteristics
Over the Operating Range ^{[8, 9]}
Parameter
Description
V_DD
V_DDQ
V_OH
Power supply voltage
I/O supply voltage
Output HIGH voltage
V_OL
Output LOW voltage
V_IH
Input HIGH voltage
V_IL
Input LOW voltage^[8]
I_X
Input leakage current
except ZZ and MODE
Input current of MODE
Input current of ZZ
I_OZ
Output leakage current
I_DD
V_DD operating supply
current
Test Conditions
for 3.3 V I/O, I_OH = –4.0 mA
for 2.5 V I/O, I_OH = –1.0 mA
for 3.3 V I/O, I_OL = 8.0 mA
for 2.5 V I/O, I_OL = 1.0 mA
for 3.3 V I/O
for 2.5 V I/O
for 3.3 V I/O
for 2.5 V I/O
GND  V_I  V_DDQ
Input = V_SS
Input = V_DD
Input = V_SS
Input = V_DD
GND  V_I  V_DDQ, output disabled
V_DD = Max, I_OUT = 0 mA,
f = f_MAX= 1/t_CYC
7.5 ns cycle, 133 MHz
10 ns cycle, 100 MHz
Min
3.135
2.375
2.4
2.0
–
–
2.0
1.7
–0.3
–0.3
5
–30
–
–5
–
–5
–
–
Max Unit
3.6
V
V_DD
V
–
V
–
V
0.4
V
0.4
V
V_DD + 0.3 V V
V_DD + 0.3 V V
0.8
V
0.7
V
5
A
–
A
5
A
–
A
30
A
5
A
225
mA
205
mA
Notes
8. Overshoot: V_IH(AC) < V_DD + 1.5 V (Pulse width less than t_CYC/2), undershoot: V_IL(AC) > –2 V (Pulse width less than t_CYC/2).
9. T_{power up}: Assumes a linear ramp from 0 V to V_DD(min) within 200 ms. During this time V_IH < V_DD and V_DDQ < V_DD.
Document Number: 38-05518 Rev. *H
Page 10 of 21
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