CY62157E_13 Datasheet, PDF (10/18 Pages) Cypress Semiconductor – 8-Mbit (512 K x 16) Static RAM

CY62157E MoBL^®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 2 (CE₁ or CE₂ Controlled) ^{[28, 29, 30]}
t_WC
ADDRESS
CE₁
t_SCE
CE₂
WE
t_SA
t_AW
t_HA
t_PWE
BHE/BLE
t_BW
OE
DATA I/O NOTE 31
t_HZOE
t_HD
t_SD
VALID DATA
Notes
28. The internal write time of the memory is defined by the overlap of WE, CE₁ = V_IL, BHE, BLE, or both = V_IL, and CE₂ = V_IH. All signals must be active to initiate
a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
29. Data I/O is high impedance if OE = V_IH.
30. If CE₁ goes HIGH and CE₂ goes LOW simultaneously with WE = V_IH, the output remains in a high impedance state.
31. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05695 Rev. *I
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