W48C111-16 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – Frequency Generator for Integrated Core Logic

PRELIMINARY
W48C111-16
Frequency Generator for Integrated Core Logic
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Power-on default to spread mode
• Two copies of CPU output
• Six copies of PCI output (synchronous w/CPU outputs)
• One copy of 48-MHz USB output
• One Buffered copy of 14.318-MHz input reference signal
• Supports 100-MHz or 66-MHz CPU operation
• Power management control input pins
• Low Frequency Test Mode
• Available in 28-pin SSOP (209 mil)
Key Specifications
Supply Voltages: ....................................... V_DDQ3 = 3.3V±5%
V_DDQ2 = 2.5V±5%
Block Diagram
VDDQ3
REF
X1
XTAL
X2
OSC
PLL Ref Freq
CPU_STOP#
SEL100/66#
PLL 1
Stop
Clock
Control
÷2/÷3
PCI_STOP#
Stop
Clock
Control
PWR_DWN#
Power
Down
Control
PLL 2
VDDQ2
CPU0
CPU1
VDDQ3
PCI_F
PCI1
PCI2
PCI3
VDDQ3
PCI4
PCI5
VDDQ3
48MHz
CPU0:1 Skew: ............................................................ 175 ps
CPU0:1 Cycle to Cycle Jitter: ..................................... 200 ps
PCI_F, PCI1:5 Skew: ...................................................500 ps
PCI_F, PCI1:5 Cycle to Cycle Jitter: ............................ 250 ps
CPU to PCI Skew: ........................ 1.5 to 4.0 ns (CPU Leads)
Output Duty Cycle: .................................................... 45/55%
PCI_F, PCI Edge Rate: .............................................. >1 V/ns
CPU_STOP#, PWR_DWN#, PCI_STOP#: 250-kΩ pull-up
resistor
Table 1. Pin Selectable Frequency
SEL100/66#
CPU(0:1)
PCI
0
66.6 MHz
33.3
1
100 MHz
33.3
Spread%
±0.5%
±0.5%
Pin Configuration
X1
1
28
X2
2
27
GND
3
26
PCI_F
4
25
PCI1
5
24
VDDQ3
6
23
PCI2
7
22
PCI3
8
21
VDDQ3
9
20
PCI4
10
19
PCI5
11
18
GND
12
17
VDDQ3
13
16
GND
14
15
GND
VDDQ3
REF
VDDQ2
CPU0
CPU1
GND
VDDQ3
GND
PCI_STOP#
CPU_STOP#
PWR_DWN#
48MHz
SEL100/66#
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 2, 1999, rev. **