W182 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – Full Feature Peak Reducing EMI Solution

W182
Full Feature Peak Reducing EMI Solution
Features
Table 1. Modulation Width Selection
• Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the
output
• Selectable output frequency range
• Single 1.25% or 3.75% down or center spread output
• Integrated loop filter components
• Operates with a 3.3 or 5V supply
• Low power CMOS design
• Available in 14-pin SOIC (Small Outline Integrated
Circuit)
Key Specifications
Supply Voltages: ........................................... V_DD = 3.3V±5%
or V_DD = 5V±10%
Frequency Range: .............................. 8 MHz ≤ F_in ≤ 28 MHz
Cycle to Cycle Jitter: ........................................ 300 ps (max.)
SS%
0
1
W182
Output
F_in ≥ F_out ≥ F_in
– 1.25%
F_in ≥ F_out ≥ F_in
– 3.75%
W182-5
Output
F_in + 0.625% ≥ F_in≥
– 0.625%
F_in + 1.875% ≥ F_in≥
–1.875%
Table 2. Frequency Range Selection
FS2
FS1
0
0
0
1
1
0
1
1
Frequency Range
8 MHz ≤ F_IN ≤ 10 MHz
10 MHz ≤ F_IN ≤ 15 MHz
15 MHz ≤ F_IN ≤ 18 MHz
18 MHz ≤ F_IN ≤ 28 MHz
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
Simplified Block Diagram
3.3V or 5.0V
Pin Configuration
SOIC
XTAL
Input
X1
X2
W182
Spread Spectrum
Output
(EMI suppressed)
FS2 1
CLKIN or X1 2
NC or X2 3
GND 4
GND 5
SS% 6
FS1 7
14 REFOUT
13 OE#
12 SSON#
11 Reset
10 ^VDD
9 VDD
8 CLKOUT
3.3V or 5.0V
Oscillator or
Reference Input
W182
Spread Spectrum
Output
(EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
June 8, 2000, rev. *A