W155 Datasheet, PDF (1/6 Pages) Cypress Semiconductor – Spread Spectrum Frequency Timing Generator

W155
Spread Spectrum Frequency Timing Generator
Features
• Generates a spread spectrum timing signal (SYSCLK)
and a non-spread signal (USBCLK)
• Requires a 14.318-MHz crystal for operation
• Supports MIPS microprocessor clock frequencies
• Reduces peak EMI by as much as 12 dB
• Integrated loop filter components
• Cycle-to-cycle jitter = 250 ps (max)
• Operates with a 3.3 or 5.0V power supply
• Spread output is selectable from 10 to 133 MHz
• TEST mode supports modulation off (High-Z) and spe-
cial test input reference frequency
• Guaranteed 45/55 duty cycle
• Packaged in a 16-pin, 300-mil-wide SOIC (Small Outline
Integrated Circuit)
Overview
The W155 incorporates the latest advances in PLL-based
spread spectrum frequency synthesizer technology. By fre-
quency modulating the SYSCLK output with a low-frequency
carrier, peak EMI can be greatly reduced in a system. Use of
this technique allows systems to pass increasingly difficult EMI
testing without resorting to costly shielding or redesign.
In a system that uses the W155, not only is EMI reduced in the
various clock lines, but also in all signals which are synchro-
nized to SYSCLK. Therefore, the benefits of using this tech-
nique increase with the number of address and data lines in
the system.
The W155 is specifically targeted toward MIPS microproces-
sor based systems where EMI is of particular concern. Each
device uses a single 14.318-MHz crystal to generate a select-
able spread spectrum output and an unmodulated 48-MHz
USB Output.
The spreading function can be disabled by taking the SSON#
pin high. Spread percentage can be selected with the SS%
input (see Table 2 below).
Table 1. Frequency Selection (14.318-MHz Reference)
SYSCLK
FS3
FS2
FS1
FS0
(Output Freq.)
0
0
0
0
133.3 MHz
0
0
0
1
120 MHz
0
0
1
0
100 MHz
0
0
1
1
74.77 MHz
0
1
0
0
70 MHz
0
1
0
1
66.6 MHz
0
1
1
0
60 MHz
0
1
1
1
50 MHz
1
0
0
0
40 MHz
1
0
0
1
33.33 MHz
1
0
1
0
30 MHz
1
0
1
1
25 MHz
1
1
0
0
20 MHz
1
1
0
1
16.67 MHz
1
1
1
0
12 MHz
1
1
1
1
10 MHz
Table 2. Spread Percentage Selection
SS%
0
1
Spread Percentage
–1.25%
–3.75%
[1]
Pin Configuration
VDD
1
X1
2
X2
3
GND
4
FS3*
5
VDD
6
FS2*
7
FS1*
8
16
TEST
15
VDD
14
USBCLK/SS%*
13
GND
12
SYSCLK
11
GND
10
FS0*
9
SSON#^
Note:
1. Internal pull-up resistor present on inputs marked with ‘*’ and pull-down
resistor present on input marked with ‘^’.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
September 29, 1999, rev. **