W133 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – Spread Spectrum System Frequency Synthesizer

PRELIMINARY
W133
Spread Spectrum System Frequency Synthesizer
Features
• Maximized EMI suppression using Cypress’s spread
spectrum technology
• Intel CK98 Specification compliant
• 0.5% downspread outputs deliver up to 10 dB lower EMI
• Four skew-controlled copies of CPU output
• Eight copies of PCI output (synchronous w/CPU output)
• Four copies of 66-MHz fixed frequency 3.3V clock
• Two copies of CPU/2 outputs for synchronous memory
reference
• Three copies of 16.67-MHz IOAPIC clock, synchronous
to CPU clock
• One copy of 48-MHz USB output
• Two copies of 14.31818-MHz reference clock
• Programmable to 133- or 100-MHz operation
• Power management control pins for clock stop and shut
down
• Available in 56-pin SSOP
Key Specifications
Supply Voltages: ...................................... V_DDQ3 = 3.3V±5%
V_DDQ2 = 2.5V±5%
Block Diagram
CPU Output Jitter: ...................................................... 250 ps
CPUdiv2 Output Jitter:.................................................250 ps
48 MHz, 3V66, PCI, IOAPIC Output Jitter: .................. 500 ps
CPU0:3, CPUdiv2_ 0:1 Output Skew: ......................... 175 ps
PCI_F, PCI1:7 Output Skew: .......................................500 ps
3V66_0:3, IOAPIC0:2 Output Skew; ...........................250 ps
CPU to 3V66 Output Offset: ............. 0.0–1.5 ns (CPU leads)
3V66 to PCI Output Offset:.............. 1.5–4.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ......... 1.5–4.0 ns (CPU leads)
Logic inputs, except SEL133/100#, have 250-kΩ pull-up
resistors.
Table 1. Pin Selectable Frequency^[1]
SEL133/100#
CPU0:3 (MHz)
PCI
1
133 MHz
33.3 MHz
0
100 MHz
33.3 MHz
Note:
1. See Table 2 for complete mode selection details.
Pin Configuration
X1
X2
CPU_STOP#
SPREAD#
SEL0
SEL1
SEL133/100#
PWRDWN#
PCI_STOP#
XTAL
OSC
2
REF0:1
PLL 1
Power
Down
Logic
STOP
Clock
Logic
÷2
÷2/÷1.5
STOP
Clock
Logic
STOP
÷2
Clock
Logic
÷2
4
CPU0:3
2
CPUdiv2_0:1
4
3V66_0:3
1
PCI_F
7
PCI1:7
3
IOAPIC0:2
GND 1
REF0 2
REF1 3
VDDQ3 4
X1 5
X2 6
GND 7
PCI_F 8
PCI1 9
VDDQ3 10
PCI2 11
PCI3 12
GND 13
PCI4 14
PCI5 15
VDDQ3 16
PCI6 17
PCI7 18
GND 19
GND 20
3V66_0 21
3V66_1 22
VDDQ3 23
GND 24
3V66_2 25
3V66_3 26
VDDQ3 27
SEL133/100# 28
56 VDDQ2
55 IOAPIC2
54 IOAPIC1
53 IOAPIC0
52 GND
51 VDDQ2
50 CPUdiv2_1
49 CPUdiv2_0
48 GND
47 VDDQ2
46 CPU3
45 CPU2
44 GND
43 VDDQ2
42 CPU1
41 CPU0
40 GND
39 VDDQ3
38 GND
37 PCI_STOP#
36 CPU_STOP#
35 PWRDWN#
34 SPREAD#
33 SEL1
32 SEL0
31 VDDQ3
30 48MHz
29 GND
Three-state
Logic
PLL2
1
48MHz
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 13, 1999, rev. **