SC660E Datasheet, PDF (1/8 Pages) Cypress Semiconductor – SMBus System Clock Buffer for Mobile Applications

SC660E
SMBus System Clock Buffer for Mobile Applications
Product Features
§ 10 output buffers for high clock fanout applications
§ Each output can be internally disabled for EMI and
power consumption reduction.
§ Separate power supply for each group of 2 clock
outputs for mixed voltage application.
§ < 250ps skew between output clocks.
§ 28-pin SSOP package for minimum board space
§ Single output Tristate pin for testability
Block Diagram
FIN
VDD
SDATA
SCLOCK
I2C
OE
VDDB
SDRAM(0:1)
SDRAM(2:3)
SDRAM4
SDRAM5
SDRAM(6:7)
SDRAM(8:9)
Product Description
The device is a high fanout system clock distributor. Its
primary application is to create the large quantity of
clocks needed to support a wide range of clock loads
that are referenced to a single existing clock. Loads of
up to 30 pF are supported. Primary application of this
component is where long traces are used to transport
clocks from their generating devices to their loads. The
creation of EMI and the degradation of waveform rise
and fall times is greatly reduced by running a single
reference clock trace to this device and then using it to
regenerate the clock that drives shorter traces by using
the SC660 to generate the clocks at the target devices
EMI is therefore minimized and board real estate is
saved.
Pin Configuration
VDDB ¹
SDRAM0 ²
SDRAM1 ³
VSS ⁴
VDDB ⁵
SDRAM2 ⁶
SDRAM3 ⁷
VSS ⁸
FIN ⁹
VDDB ¹⁰
SDRAM4 ¹¹
VSS ¹²
VDD ¹³
SDATA ¹⁴
28 _VDDB
27 _SDRAM9
26 _SDRAM8
25 _VSS
24 _VDDB
23 _SDRAM7
22 _SDRAM6
21 _VSS
20 _OE
19 _VDDB
18 _SDRAM5
17 _VSS
16 _VSS
15 _SCLOCK
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134. Tel: [phone]
http://www.cypress.com
Document#: 38-07025 Rev. *A
12/17/2002
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