S6J311E Datasheet, PDF (1/116 Pages) Cypress Semiconductor – 32-Bit Traveo™ Family S6J3110 Series Microcontroller Datasheet

S6J311E, S6J311D, S6J311C, S6J311B
32-Bit Traveo™ Family
S6J3110 Series Microcontroller Datasheet
The S6J3110 series is a set of 32-bit microcontrollers designed for in-vehicle use. It uses the ARM^® Cortex-R5 CPU as a CPU.
Features
This section explains the features of the S6J3110 series.
Cortex-R5 Core
This section explains the Cortex-R5 CPU core.
ARM^® Cortex^®-R5
32-bit ARM architecture
 2-instruction issuance super scalar
 8-stage pipeline
ARMv7/Thumb^®-2 instruction set
MPU (memory protection) equipped
 16-area support
ECC support for the TCM ports for RAM
 1-bit error correction and 2-bit error detection
(SEC-DED)
TCM ports
 2 TCM ports
• ATCM port
• BTCM port (B0TCM, B1TCM)
 Caches
 Instruction cache 16 KB
 Data cache 16 KB
VIC port
 Low latency interrupt
AXI master interface
 64-bit AXI interface (instruction/data access)
 32-bit AXI interface (I/O access)
AXI slave interface
 64-bit AXI interface (TCM port access)
ETM-R5 trace
Peripheral Functions
This section explains peripheral functions.
Clock generation
 Main clock oscillation (4 MHz)
 No sub clock oscillation
 CR oscillation (100 kHz)
 CR oscillation (4 MHz)
Built-in flash memory size
 Program: 4096 K + 64 KB (S6J311EyzC*) / 3072K + 64KB
(S6J311DyzC*) / 2048K + 64KB (S6J311CyzC*) / 1536K +
64KB (S6J311ByzC*)
 Work: 112 KB (S6J311EyzC*) / 112 KB (S6J311DyzC*) /
112 KB (S6J311CyzC*) / 112 KB (S6J311ByzC*)
* y: J/H, z: A/B
Built-in RAM size
 TCRAM 64 KB
 System SRAM 256 KB (S6J311EyzC*) / 192KB
(S6J311DyzC*) / 128KB (S6J311CyzC*) / 64KB
(S6J311ByzC*)
 Backup RAM 64 KB (S6J311EyzC*) / 64 KB
(S6J311DyzC*) / 64 KB (S6J311CyzC*) / 64 KB
(S6J311ByzC*)
* y: J/H, z: A/B
General-purpose ports: 150 channels (S6J311xJzC*)/116
channels (S6J311xHzC*)
* x: E/D/C/B, z: A/B
DMA controller
 Up to 16 channels can be activated simultaneously.
A/D converter (successive approximation type)
 12-bit resolution, 2 units mounted: Max 64 channels (32
channels + 32 channels)
External interrupt input: 16 channels
 Level ("H"/"L") and edge (rising/falling) can be detected.
Multi-function serial (transmission and reception FIFOs
mounted): Max 22 channels
<I²C>
 Full-duplex double buffering system, 64-byte transmission
FIFO, 64-byte reception FIFO.
 Standard mode ( Max. 100kbps ) is supported only.
 DMA transfer is supported (only for ch.0 to ch.7).
<UART (asynchronous serial interface)>
 Full duplex, double buffering system; 64-byte transmission
FIFO, 64-byte reception FIFO
 Parity check can be enabled/disabled.
 Built-in dedicated baud rate generator
 An external clock can be used as a transfer clock.
 Parity, frame, overrun error detection functions are
available.
 DMA transfer is supported (only for ch.0 to 7).
<CSIO (synchronous serial interface)>
 Full duplex, double buffering system; 64-byte transmission
FIFO, 64-byte reception FIFO
 Support for SPI. Both master and slave roles are supported.
Data length in bits can be set to a value from 5 to 16 or one
of the values of 20, 24, and 32.
 Built-in dedicated baud rate generator (master operation)
 External clock input is enabled (slave operation).
Cypress Semiconductor Corporation
Document Number: 002-05681 Rev.*A
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised June 20, 2016