S6E2C1 Datasheet, PDF (1/191 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M4F FM4 Microcontroller

S6E2C1 Series
32-bit ARM^® Cortex^®-M4F
FM4 Microcontroller
Devices in the S6E2C1 Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This
series is based on the ARM Cortex-M4F processor with on-chip flash memory and SRAM. The series has peripherals such as
motor control timers, A/D converters, and communications interfaces (USB, CAN, UART, CSIO (SPI), I²C, LIN). The products that
are described in this data sheet are placed into TYPE3-M4 product categories "FM4 Family Peripheral Manual Main Part
(002-04856)."
Features
32-bit ARM Cortex-M4F Core
Processor version: r0p1
Up to 200 MHz frequency operation
FPU built-in
Support DSP instructions
Memory protection unit (MPU): improves the reliability of an
embedded system
Integrated nested vectored interrupt controller (NVIC): 1 NMI
(non-maskable interrupt) and 128 peripheral interrupts and
16 priority levels
24-bit system timer (Sys Tick): system timer for OS task
management
External Bus Interface
Supports SRAM, NOR, NAND flash and SDRAM device
Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
8-/16-/32-bit data width
Up to 25-bit address bus
Supports address/data multiplexing
Supports external RDY function
Supports scramble function
 Possible to set the validity/invalidity of the scramble
function for the external areas 0x6000_0000 to
0xDFFF_FFFF in 4 Mbytes units.
 Possible to set two kinds of the scramble key
 Note: It is necessary to use the Cypress provided software
library to use the scramble function.
On-chip Memories
Flash memory
This series is based on two independent on-chip flash
memories.
 Up to 2048 Kbytes
 Built-in flash accelerator system with 16 Kbytes trace buffer
memory
 Read access to flash memory that can be achieved without
wait-cycle up to an operating frequency of 72 MHz. Even at
the operating frequency more than 72 MHz, an equivalent
single cycle access to flash memory can be obtained by
the flash accelerator system.
 Security function for code protection
 SRAM
This is composed of three independent SRAMs (SRAM0,
SRAM1 and SRAM2). SRAM0 is connected to the I-code bus
and D-code bus of Cortex-M4F core. SRAM1 and SRAM2
are connected to system bus of Cortex-M4F core.
 SRAM0: up to 192 Kbytes
 SRAM1: 32 Kbytes
 SRAM2: 32 Kbytes
Multi-function Serial Interface (Max 16 Channels)
Separate 64 byte receive and transmit FIFO buffers for
channels 0 to 7.
Operation mode is selectable for each channel from the
following:
 UART
 CSIO (SPI)
 LIN
 I²C
 UART
 Full-duplex double buffer
 Selection with or without parity supported
 Built-in dedicated baud rate generator
 External clock available as a serial clock
 Various error detect functions available (parity errors,
framing errors, and overrun errors)
CSIO (SPI)
 Full-duplex double buffer
 Built-in dedicated baud rate generator
 Overrun error detect function available
 Serial chip select function (ch 6 and ch 7 only)
 Supports high-speed SPI (ch 4 and ch 6 only)
 Data length 5 to 16-bit
Cypress Semiconductor Corporation
Document Number: 002-05032 Rev.*A
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised February 5, 2016