PLDC20G10B Datasheet, PDF (1/14 Pages) Cypress Semiconductor – CMOS Generic 24-Pin Reprogrammable Logic Device

USE ULTRA37000™ FOR
ALL NEW DESIGNS
PLDC20G10B
PLDC20G10
CMOS Generic 24-Pin Reprogrammable
Logic Device
Features
• Fast
— Commercial: t_PD = 15 ns, t_CO = 10 ns, t_S = 12 ns
— Military: t_PD = 20 ns, t_CO = 15 ns, t_S = 15 ns
• Low power
— I_CC max.: 70 mA, commercial
— I_CC max.: 100 mA, military
• Commercial and military temperature range
• User-programmable output cells
— Selectable for registered or combinatorial operation
— Output polarity control
— Output enable source selectable from pin 13 or
product term
• Generic architecture to replace standard logic
functions including: 20L10, 20L8, 20R8, 20R6, 20R4,
12L10, 14L8, 16L6, 18L4, 20L2, and 20V8
• Eight product terms and one OE product term per output
Logic Block Diagram
V_SS
I
I
I
12
11
10
9
I
I
8
7
• CMOS EPROM technology for reprogrammability
• Highly reliable
— Uses proven EPROM technology
— Fully AC and DC tested
— Security feature prevents logic pattern duplication
— ±10% power supply voltage and higher noise
immunity
Functional Description
Cypress PLD devices are high-speed electrically program-
mable logic devices. These devices utilize the sum-of-products
(AND-OR) structure providing users the ability to program
custom logic functions for unique requirements.
In an unprogrammed state the AND gates are connected via
EPROM cells to both the true and complement of every input.
By selectively programming the EPROM cells, AND gates may
be connected to either the true or complement or disconnected
from both true and complement inputs.
I
I
I
I
I
CP/I
6
5
4
3
2
1
PROGRAMMABLE
AND ARRAY
8
8
8
8
8
8
8
8
8
8
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
13
14
15
16
17
18
19
20
21
22
23
24
I/OE
I/O ₉
I/O ₈
I/O ₇
I/O ₆
I/O ₅
I/O ₄
I/O ₃
I/O ₂
I/O ₁
I/O ₀
V _CC
Pin Configurations
LCC
Top View
STD PLCC
Top View
JEDEC PLCC ^[1]
Top View
4 3 2 1 282726
I5
25 NC
I6
24 I/O ₂
I
I
I
7
8
9
PLDC20G10
PLDC20G10B
23
22
21
I/O ₃
I/O ₄
I/O ₅
I 10
20 I/O 6
NC 11
19 I/O ₇
12131415161718
4 3 2 1 2827 26
NC ⁵
25 I/O 2
I6
24 I/O3
I ⁷ PLDC20G10 23 ^I/O 4
NC ⁸ PLDC20G10B 22 ^I/O5
I9
21 ^I/O 6
I 10
20 I/O7
NC ¹¹ _{121314 1516 171819} ^NC
4 3 2 1 2827 26
I5
25 I/O2
I6
24 I/O3
I ⁷ _{CG7C323–A} 23 ^I/O4
NC 8 _{CG7C323B–A} 22 NC
I9
21 ^I/O5
I 10
20 I/O 6
I ¹¹ _{121314 1516 171819} ^I/O 7
Note:
1. The CG7C323 is the PLDC20G10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The
difference is in the location of the “no connect” or NC pins.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03010 Rev. *A
Revised April 20, 2004