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MB95810K Datasheet, PDF (1/121 Pages) Cypress Semiconductor – New 8FX 8-bit Microcontrollers | |||
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MB95810K Series
New 8FX 8-bit Microcontrollers
The MB95810K Series is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the
microcontrollers of these series contain a variety of peripheral resources.
Features
â F2MC-8FX CPU core
â Instruction set optimized for controllers
⢠Multiplication and division instructions
⢠16-bit arithmetic operations
⢠Bit test branch instructions
⢠Bit manipulation instructions, etc.
â Clock
â Selectable main clock source
⢠Main oscillation clock (up to 16.25 MHz, maximum ma-
chine clock frequency: 8.125 MHz)
⢠External clock (up to 32.5 MHz, maximum machine clock
frequency: 16.25 MHz)
⢠Main CR clock (4 MHz ï±2%)
⢠Main CR PLL clock
- The main CR PLL clock frequency becomes 8 MHz
ï±2% when the PLL multiplication rate is 2.
- The main CR PLL clock frequency becomes 10 MHz
ï±2% when the PLL multiplication rate is 2.5.
- The main CR PLL clock frequency becomes 12 MHz
ï±2% when the PLL multiplication rate is 3.
- The main CR PLL clock frequency becomes 16 MHz
ï±2% when the PLL multiplication rate is 4.
â Selectable subclock source
⢠Suboscillation clock (32.768 kHz)
⢠External clock (32.768 kHz)
⢠Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz)
â Timer
â 8/16-bit composite timer ï´ 2 channels
â 8/16-bit PPG ï´ 2 channels
â 16-bit PPG timer ï´ 2 channels
â 16-bit reload timer ï´ 1 channel
â Time-base timer ï´ 1 channel
â Watch prescaler ï´ 1 channel
â UART/SIO ï´ 1 channel
â Full duplex double buffer
â Capable of clock asynchronous (UART) serial data transfer
and clock synchronous (SIO) serial data transfer
â I2C bus interface ï´ 1 channel
â Built-in wake-up function
â LIN-UART
â Full duplex double buffer
â Capable of clock asynchronous serial data transfer and clock
synchronous serial data transfer
â External interrupt ï´ 12 channels
â Interrupt by edge detection (rising edge, falling edge, and
both edges can be selected)
â Can be used to wake up the device from different low power
consumption (standby) modes
â 8/10-bit A/D converter ï´ 12 channels
â 8-bit or 10-bit resolution can be selected.
â Low power consumption (standby) modes
â There are four standby modes as follows:
⢠Stop mode
⢠Sleep mode
⢠Watch mode
⢠Time-base timer mode
â In standby mode, two further options can be selected: normal
standby mode and deep standby mode.
â I/O port (no. of I/O ports: 58)
â General-purpose I/O ports (CMOS I/O): 54
â General-purpose I/O ports (N-ch open drain): 4
â On-chip debug
â 1-wire serial control
â Serial writing supported (asynchronous mode)
â Hardware/software watchdog timer
â Built-in hardware watchdog timer
â Built-in software watchdog timer
â Power-on reset
â A power-on reset is generated when the power is switched
on.
â Low-voltage detection (LVD) reset circuit
â The LVD function is enabled by default. For details, see â18.2
Recommended Operating Conditionsâ in
âElectrical Characteristicsâ.
â The LVD function can be controlled through software.
â The LVD reset circuit control register (LVDCC) enables or
disables the LVD reset.
â The LVD reset circuit has an internal low-voltage detector.
The combination of detection voltage and release voltage
can be selected from four options.
â Comparator ï´ 2 channels
â Built-in dedicated BGR
â The comparator reference voltage can be selected between
the BGR voltage and the comparator pin.
â Clock supervisor counter
â Built-in clock supervisor counter
â Dual operation Flash memory
â The program/erase operation and the read operation can be
executed in different banks (upper bank/lower bank) simul-
taneously.
â Flash memory security function
â Protects the content of the Flash memory.
Cypress Semiconductor Corporation ⢠198 Champion Court
Document Number: 002-04694 Rev. *A
⢠San Jose, CA 95134-1709 ⢠408-943-2600
Revised March 29, 2016
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