CYWB0224ABS_09 Datasheet, PDF (1/6 Pages) Cypress Semiconductor – West Bridge Astoria

ADVANCE INFORMATION
CYWB0224ABS/CYWB0224ABM
West Bridge^TM Astoria^TM
Features
■ N-Xpress™ NAND Controller Technology
❐ Interleave up to 16 NANDs with 8 Chip Enables (CE#) for
x8 or x16 SLC (CYWB0224ABS) or MLC
(CYWB0224ABM) NAND flash devices.
❐ 4-bit Error Correction Coding
❐ Bad Block Management
❐ Static Wear Leveling
■ Multimedia Device Support
❐ Up to 2 SD/SDIO/MMC/MMC+/CE-ATA devices
■ SLIM™ Architecture, allowing simultaneous and
independent data paths between the processor and USB,
and between the USB and Mass Storage.
■ Fully backward compatible (including pin to pin) to Antioch
(CYWB0124AB)
■ High speed USB at 480 Mbps
❐ USB 2.0 compliant
❐ Integrated USB 2.0 transceiver, smart Serial Interface
Engine
❐ 16 programmable endpoints
■ Flexible Processor Interface, which supports:
❐ Multiplexing and nonMultiplexing Address and Data
interface
❐ SRAM Interface
❐ Pseudo CRAM interface (Antioch Interface)
❐ Pseudo NAND Flash interface
❐ SPI (slave mode) interface
❐ DMA slave support
■ Ultra low power, 1.8V core operation
■ Low Power Modes
■ Small footprint, 6x6mm VFBGA
■ Supports I2C boot and Processor Boot
■ Selectable Clock Input Frequencies
❐ 19.2 MHz, 24 MHz, 26 MHz, and 48 MHz
Applications
■ Cellular Phones
■ Portable Media Players
■ Personal Digital Assistants
■ Portable Navigation Devices
■ Digital Cameras
■ POS Terminals
■ Portable Video Recorders
Logic Block Diagram
West Bridge^TM Astoria^TM
Control
Registers
uC
Access Control
P
U
SLIM^TM
SD/SDIO/ Cypress
MMC+/ CE- N-Xpress^TM
ATA Block Engine
Configurable Storage
Interface
S
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-11710 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 7, 2007
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