CYWB012X Datasheet, PDF (1/9 Pages) Cypress Semiconductor – West Bridge Antioch Memory-mapped interface to main processor

ADVANCE
INFORMATION
CYWB012X Family
West Bridge^® Antioch™
West Bridge® Antioch™
Features
■ SLIM^® architecture, allowing simultaneous and independent
data paths between processor and USB, and between USB
and mass storage
■ High speed USB at 480 Mbps
❐ USB 2.0 compliant
❐ Integrated USB 2.0 transceiver, smart Serial Interface Engine
❐ 16 programmable endpoints
■ Mass storage device support
❐ MMC/MMC+/SD
❐ NAND Flash: × 8 or × 16, SLC
❐ Full NAND management (ECC, wear-leveling)
■ Memory-mapped interface to main processor
■ DMA slave support
■ Ultra low power, 1.8 V core operation
■ Small footprint, 6 × 6 mm VFBGA and WLCSP
■ Selectable clock input frequencies
❐ 19.2 MHz, 24 MHz, 48 MHz
■ Expanded mass storage device support
❐ MMC/MMC+/SD
❐ CE-ATA for micro-HDD
❐ NAND Flash: × 8 or × 16, SLC
❐ Full NAND management (ECC, wear-leveling)
■ Expanded selectable clock input frequencies
❐ 19.2 MHz, 24 MHz, 26 MHz, 48 MHz
Applications
■ Cellular Phones
■ Portable Media Players
■ Personal Digital Assistants
■ Digital Cameras
■ Portable Video Recorder
Logic Block Diagram
West Bridge Antioch
Control Registers 8051 MCU
Access Control
P
U
SLIM^TM
Mass Storage Interface
SD/MMC/CE-ATA
NAND
S
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-05898 Rev.*C
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 14, 2011
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