CYWB0124AB_09 Datasheet, PDF (1/2 Pages) Cypress Semiconductor – West Bridge,Antioch,USB/Mass Storage Peripheral Controller

CYWB0124AB
West Bridge™ : Antioch™ USB/Mass
Storage Peripheral Controller
1.0 Features
• SLIM™ Architecture, allowing simultaneous and
independent data paths between Processor & USB and
between USB & Mass Storage
• High-Speed USB at 480 Mbps
— USB 2.0 compliant
— Integrated USB 2.0 transceiver, smart Serial Interface
Engine
— 16 programmable endpoints
• Mass Storage device support
— MMC/MMC+/SD
— NAND flash: x8 or x16, SLC
— Full NAND management (ECC, wear-leveling)
• Memory-mapped interface to main processor
• DMA slave support
• Ultra low-power, 1.8V core operation
• Low Power Modes
• Small footprint, 6x6mm VFBGA
• Selectable Clock Input Frequencies
— 19.2 MHz, 24 MHz, 26 MHz, 48 MHz
2.0 Applications
• Cellular Phones
• Portable Media Players
• Personal Digital Assistants
• Digital Cameras
• Portable Video Recorder
Figure 1-1. West Bridge Antioch Block Diagram
West Bridge Antioch
Control Registers 8051 MCU
Access Control
P
U
SLIM^TM
Mass Storage Interface
SD/MMC/CE-ATA
NAND
S
3.0 Functional Overview
3.1The SLIM™ architecture
The Simultaneous Link to Independent Multimedia (SLIM)
architecture allows three different interfaces (the P-port, the
S-port and the U-port) to connect to one-another indepen-
dently.
With this architecture, connecting a device using Antioch to a
PC through USB does not disturb any of the functions of the
device, which can still access Mass storage at the same time
the PC is synchronizing with the main processor.
The SLIM architecture enables new usage models, in which a
PC can access a Mass storage device independent of the
main processor, or enumerate access to both the mass
storage and the main processor at the same time.
Cypress Semiconductor Corporation
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised October 24, 2006