CYU01M16ZFC Datasheet, PDF (1/14 Pages) Cypress Semiconductor – 16-Mbit (1M x 16) Pseudo Static RAM

PRELIMINARY
CYU01M16ZFC
MoBL3™
16-Mbit (1M x 16) Pseudo Static RAM
Features
• Wide voltage range: 1.7V–1.95V
• Access Time: 70 ns
• Ultra-low active power
— Typical active current: 3 mA @ f = 1 MHz
— Typical active current: 18 mA @ f = f_max
• Ultra low standby power
• 16-word Page Mode
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Deep Sleep Mode
• Offered in a Lead-Free 48-ball BGA Package
• Operating Temperature: –40°C to +85°C
Functional Description^[1]
The CYU01M16ZFC is a high-performance CMOS Pseudo
Static RAM organized as 1M words by 16 bits that supports an
asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL^®) in
portable applications such as cellular telephones. The device
can be put into standby mode when deselected (CE HIGH or
both BHE and BLE are HIGH). The input/output pins (I/O₀
through I/O₁₅) are placed in a high-impedance state when:
deselected (CE HIGH), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW and WE
LOW).
Writing to the device is accomplished by taking Chip Enable
(CE LOW) and Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O₀ through
I/O₇), is written into the location specified on the address pins
(A₀ through A₁₉). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O₈ through I/O₁₅) is written into the location
specified on the address pins (A₀ through A₁₉).
Reading from the device is accomplished by taking Chip
Enables (CE LOW) and Output Enable (OE) LOW while
forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE)
is LOW, then data from the memory location specified by the
address pins will appear on I/O₀ to I/O₇. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O₈ to
I/O₁₅. Refer to the truth table for a complete description of read
and write modes.
Deep Sleep Mode is enabled by driving ZZ LOW. See the Truth
Table for a complete description of Read, Write, and Deep
Sleep mode.
Logic Block Diagram
DATA IN DRIVERS
A
A
8
9
A₁₀
A₁₁
A₁₂
1M × 16
A₁₃
RAM Array
A₁₄
A₁₅
A₁₆
A₁₇
A₁₈
A₁₉
COLUMN DECODER
I/O₀–I/O₇
I/O₈–I/O₁₅
Power-Down
Circuit
BHE
BLE
BHE
WE
CE
OE
BLE
ZZ
CE
Refresh/Power-down
Circuit
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05604 Rev. *F
Revised January 16, 2006