CYP15G0402DXB Datasheet, PDF (1/29 Pages) Cypress Semiconductor – Quad HOTLink II™ SERDES

CYP15G0402DXB
CYV15G0402DXB
Quad HOTLink II™ SERDES
Features
• Second-generation HOTLink^® technology
• Compliant to multiple standards
— Fibre Channel, Gigabit Ethernet (IEEE802.3z), ES-
CON^® and DVB-ASI
— CYV15G0402DXB compliant to SMPTE 259M and
SMPTE 292M
• Quad-channel transceiver operates from 195 to 1500
Mbps serial data rate
— Aggregate throughput of 12 Gbps
• 10-bit unencoded data transport
• Selectable parity check/generate
• Four independent 10-bit channels with separate Clock
and Data Recovery for each channel
• Selectable input clocking options
• MultiFrame™ Receive Framer
— Comma or full K28.5 detect
— Single or Multi-Byte framer for byte alignment
— Low-latency option
• Synchronous LVTTL parallel interface
• Internal phase-locked loops (PLLs) with no external
PLL components
• Optional Phase Align Buffer in Transmit Path
• Differential PECL-compatible serial inputs
• Differential PECL-compatible serial outputs
— Source matched for 50Ω transmission lines
— No external resistors required
— Signaling rate controlled edge rates
• Compatible with
— Fiber-optic modules
— Copper cables
— Circuit board traces
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Per-channel Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low-power 2.5W @3.3V typical
• Single 3.3V supply
• 256-ball thermally enhanced BGA
• Pb-Free package option available
• 0.25µ BiCMOS technology
Functional Description
The CYP(V)15G0402DXB^[1] Quad HOTLink II™ SERDES is a
point-to-point communications building block allowing the
transfer of preencoded data over high-speed serial links
(optical fiber, balanced, and unbalanced copper transmission
lines) at signaling speeds ranging from 195 to 1500 MBaud per
serial link.
Each transmit channel accepts preencoded 10-bit trans-
mission characters in an Input Register, serializes each
character, and drives it out a PECL-compatible differential line
driver. Each receive channel accepts a serial data stream at a
differential line receiver, deserializes the stream into 10-bit
characters, optionally frames these characters to the proper
10-bit character boundaries and presents these characters to
an Output register. Figure 1 illustrates typical connections
between independent systems and a CYP(V)15G0402DXB.
The CYV15G0402DXB satisfies the SMPTE-259M and
SMPTE-292M compliance as per the EG34-1999 Pathological
Test Requirements.
10
10
10
10
Serial Links
Serial Links
Independent
Channel
Transceiver
Independent
Channel
Transceiver
10
10
10
10
10
10
Serial Links
Independent
Channel
Transceiver
10
10
Independent
10
10
Serial Links
Channel
10
10
Cable or
Transceiver
Optical
Connections
Figure 1. CYP(V)15G0402DXB HOTLink II™ System Connections
Note:
1. CYV15G0402DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYP15G0402DXB refers to devices that are not compliant to SMPTE 259M
and SMPTE 292M pathological test requirements. CYP(V)15G0402DXB refers to both devices.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02057 Rev. *G
Revised March 31, 2005