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CYM1836 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – 128K x 32 Static RAM Module
CYM1836
Features
• High-density 4-megabit SRAM module
• 32-bit standard footprint supports densities from 16K
x 32 through 1M x 32
• High-speed CMOS SRAMs
— Access time of 15 ns
• Low active power
— 2.6W (max.) at 20 ns
• SMD technology
• TTL-compatible inputs and outputs
• Low profile
— Max. height of 0.57 in.
• Small PCB footprint
— 0.78 sq. in.
• Available in SIMM, ZIP format. SIMM suitable for vertical
or angled sockets.
Functional Description
The CYM1836 is a high-performance 4-megabit static RAM
module organized as 128K words by 32 bits. This module is
128K x 32 Static RAM Module
constructed from four 128K x 8 SRAMs in SOJ packages
mounted on an epoxy laminate board with pins. Four chip se-
lects (CS1, CS2, CS3, CS4) are used to independently enable
the four bytes. Reading or writing can be executed on individ-
ual bytes or any combination of multiple bytes through proper
use of selects.
Writing to each byte is accomplished when the appropriate
Chip Select (CS) and Write Enable (WE) inputs are both
LOW. Data on the input/output pins (I/O) is written into the
memory location specified on the address pins (A0 through
A16).
Reading the device is accomplished by taking the Chip Select
(CS) LOW while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location
specified on the address pins will appear on the data in-
put/output pins (I/O).
The data input/output pins stay at the high-impedance state
when write enable is LOW or the appropriate chip selects are
HIGH.
Two pins (PD0 and PD1) are used to identify module mem-
ory density in applications where alternate versions of the
JEDEC-standard modules can be interchanged.
Logic Block Diagram
A0 − A16
OE
WE
PD0−OPEN
PD1−OPEN
17
128K x 8
SRAM
4
I/O0 − I/O7
CS1
128K x 8
SRAM
4
I/O8 − I/O15
CS2
128K x 8
SRAM
4
I/O16 − I/O23
CS3
128K x 8
SRAM
4
I/O24 − I/O31
CS4
1836–1
Pin Configuration
ZIP/SIMM
Top View
PD0
I/O0
I/O1
I/O2
I/O3
VCC
A7
A8
A9
I/O4
I/O5
I/O6
I/O7
WE
A14
CS1
CS3
A16
GND
I/O16
I/O17
I/O18
I/O19
A10
A11
A12
A13
I/O20
I/O21
I/O22
I/O23
GND
1
23
45
67
89
10 11
12 13
14 15
16 17
18 19
20 21
22 23
24 25
26 27
28 29
30 31
32
33
34 35
36 37
38 39
40 41
42 43
44 45
46 47
48 49
50 51
52 53
54 55
56 57
58 59
60 61
62 63
64
GND
PD1
I/O8
I/O9
I/O10
I/O11
A0
A1
A2
I/O12
I/O13
I/O14
I/O15
GND
A15
CS2
CS4
NC
OE
I/O24
I/O25
I/O26
I/O27
A3
A4
A5
VCC
A6
I/O28
I/O29
I/O30
I/O31
1836–2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
February 15, 1999
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