CYK256K16MCCB Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 4-Mbit (256K x 16) Pseudo Static RAM

CYK256K16MCCB
MoBL3™
4-Mbit (256K x 16) Pseudo Static RAM
Features
• Wide voltage range: 2.70V–3.30V
• Access time: 55 ns, 60 ns and 70 ns
• Ultra-low active power
— Typical active current: 1 mA @ f = 1 MHz
— Typical active current: 8 mA @ f = f_max (70-ns speed)
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in a 48-ball BGA package
Functional Description^[1]
The CYK256K16MCCB is a high-performance CMOS Pseudo
static RAM organized as 256K words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL^®) in
portable applications such as cellular telephones. The device
can be put into standby mode when deselected (CE HIGH or
both BHE and BLE are HIGH). The input/output pins (I/O₀
through I/O₁₅) are placed in a high-impedance state when:
deselected (CE HIGH), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW and WE
LOW).
Writing to the device is accomplished by taking Chip Enable
(CE LOW) and Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O₀ through
I/O₇) is written into the location specified on the address pins
(A₀ through A₁₇). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O₈ through I/O₁₅) is written into the location
specified on the address pins (A₀ through A₁₇).
Reading from the device is accomplished by taking Chip
Enable (CE LOW) and Output Enable (OE) LOW while forcing
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is
LOW, then data from the memory location specified by the
address pins will appear on I/O₀ to I/O₇. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O₈ to
I/O₁₅. Refer to the truth table for a complete description of read
and write modes.
Logic Block Diagram
A₁₀
A₉
A₈
A₇
A₆
A₅
A₄
A₃
A₂
A₁
A₀
DATA IN DRIVERS
256K × 16
RAM Array
COLUMN DECODER
I/O0 – I/O7
I/O8 – I/O15
Power- Down
Circuit
BHE
BLE
BHE
WE
CE
OE
BLE
CE
Note:
1. For best practice recommendations, please refer to the CY application note System Design Guidelines on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05585 Rev. *F
Revised October 18, 2006
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