CYD01S36V_08 Datasheet, PDF (1/28 Pages) Cypress Semiconductor – FLEx36™ 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM

CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
FLEx36™ 3.3V 32K/64K/128K/256K/512 x 36
Synchronous Dual-Port RAM
Features
Functional Description
■ True dual-ported memory cells that allow simultaneous access
of the same memory location
■ Synchronous pipelined operation
■ Family of 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit and 18-Mbit devices
■ Pipelined output mode allows fast operation
■ 0.18 micron CMOS for optimum speed and power
■ High-speed clock to data access
■ 3.3V low power
❐ Active as low as 225 mA (typ.)
❐ Standby as low as 55 mA (typ.)
■ Mailbox function for message passing
■ Global master reset
■ Separate byte enables on both ports
■ Commercial and industrial temperature ranges
■ IEEE 1149.1-compatible JTAG boundary scan
■ 256 Ball FBGA (1-mm pitch)
■ Counter wrap around control
❐ Internal mask register controls counter wrap-around
❐ Counter-interrupt flags to indicate wrap-around
❐ Memory block retransmit operation
■ Counter readback on address lines
■ Mask register readback on address lines
The FLEx36 family includes 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit, and
18-Mbit pipelined, synchronous, true dual-port static RAMs that
are high-speed, low-power 3.3V CMOS. Two ports are provided,
permitting independent, simultaneous access to any location in
memory. A particular port can write to a certain location while
another port is reading that location. The result of writing to the
same location by more than one port at the same time is
undefined. Registers on control, address, and data lines allow for
minimal setup and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CYD18S36V devices in this family has limited features.
Please see Address Counter and Mask Register Operations^[19]
on page 5 for details.
■ Dual Chip Enables on both ports for easy depth expansion
■ Seamless migration to next-generation dual-port family
Seamless Migration to Next-Generation Dual-Port
Family
Cypress offers a migration path for all devices in this family to the
next-generation devices in the Dual-Port family with a compatible
footprint. Please contact Cypress Sales for more details.
Table 1. Product Selection Guide
Density
Part Number
Max. Speed (MHz)
1 Mbit
(32K x 36)
CYD01S36V
167
2 Mbit
(64K x 36)
CYD02S36V
167
4 Mbit
(128K x 36)
CYD04S36V
167
9 Mbit
(256K x 36)
CYD09S36V
167
18 Mbit
(512K x 36)
CYD18S36V
133
Max. Access Time – Clock to Data
4.0
4.4
4.0
4.0
5.0
(ns)
Typical Operating Current (mA)
225
225
225
270
315
Package
256 FBGA
256 FBGA
256 FBGA
256 FBGA
256 FBGA
(17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm) (23 mm x 23 mm)
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06076 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 12, 2008
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